Robust Low Power VLSI ECE 7502 S2015 Delay Test ECE 7502 Class Discussion He Qi March 19, 2015

Robust Low Power VLSI Requirements Specification Architecture Logic / Circuits Physical Design Fabrication Manufacturing Test Packaging Test PCB Test System Test PCB Architecture PCB Circuits PCB Physical Design PCB Fabrication Design and Test Development Customer Validate Verify Test

Robust Low Power VLSI Intro to Delay Test  Approach  At-speed Functional Pattern  Scan Based Structural Test (Cost Effective)  Tool  Automatic Test Pattern Generator (ATPG)  Timing Aware ATPG (Expensive and Time Consuming)  Timing Unaware ATPG (Cheap and Fast)  Fault Model  Transition Fault  Slow-to-Rise  Slow-to-Fall  Path Delay Fault 3

Robust Low Power VLSI Problem of Current ATPG Approach  Timing aware ATPG is too time consuming and expensive.  Timing unaware ATPG can only detect timing violation on short path. However, long paths are more likely to fail due to small delay defects. 4

Robust Low Power VLSI Goal of This Work  Develop a new approach/automation flow to use timing unaware ATPG to detect most of the timing violation of device under test including small delay defects. 5 Ahmed, Nisar, Mohammad Tehranipoor, and Vinay Jayaram. "Timing-based delay test for screening small delay defects." In Proceedings of the 43rd annual Design Automation Conference, pp ACM, 2006.

Robust Low Power VLSI Path Length Analysis  Long Path (LP): A long path in a design is defined as a path, if affected by a small delay defect can cause a timing failure.  Short Path (SP): A short path requires a significant delay defect size that will create a very large timing variability to cause a failure.  Intermediate Path (IP): A path with a delay in the range other than long paths 6 Ahmed, Nisar, Mohammad Tehranipoor, and Vinay Jayaram. "Timing-based delay test for screening small delay defects." In Proceedings of the 43rd annual Design Automation Conference, pp ACM, 2006.

Robust Low Power VLSI Path Length Analysis  For small delay defects in short paths, high frequency is needed to detect the defects.  This work only consider delay defects in long paths and use nominal frequency of the device under test. 7 Ahmed, Nisar, Mohammad Tehranipoor, and Vinay Jayaram. "Timing-based delay test for screening small delay defects." In Proceedings of the 43rd annual Design Automation Conference, pp ACM, 2006.

Robust Low Power VLSI  The authors move the figure “right” by caring only about the endpoints that the longest path connect to them fall into the LP category.  An observation point at the end of a path (primary output or scan flip-flop) is referred to as an endpoint. 8 Ahmed, Nisar, Mohammad Tehranipoor, and Vinay Jayaram. "Timing-based delay test for screening small delay defects." In Proceedings of the 43rd annual Design Automation Conference, pp ACM, Proposed ATPG Methodology

Robust Low Power VLSI Proposed ATPG Methodology  We need to let ATPG tool only generate patterns for those endpoints. Timing unaware ATPG tools have the feature of being set to only care about specific endpoints and screen others. The authors use static timing analysis tools to get the path information and use custom script to translate this information to ATPG-readable format. 9

Robust Low Power VLSI Proposed ATPG Methodology Care only about “LP endpoints” cannot guarantee more coverage on long paths, since these endpoints also has short paths connect to them and ATPG tool tend to pick these short paths to test.  Timing unaware ATPG tools can be set to use multiple path to detect one transition delay fault site (multiple-detect), increasing the chance of involving long paths. 10

Robust Low Power VLSI Proposed ATPG Methodology After using multi-detect, still a lot short paths involved. 11 Ahmed, Nisar, Mohammad Tehranipoor, and Vinay Jayaram. "Timing-based delay test for screening small delay defects." In Proceedings of the 43rd annual Design Automation Conference, pp ACM, 2006.

Robust Low Power VLSI Proposed ATPG Methodology 12  The authors use a custom script to check which paths involved in the multi-detect process.  They 3 path types. An endpoint which observes a transition is referred to as an active endpoint. An endpoint which does not observe a transition, referred to as non-active.  non-active endpoints  active endpoints with path length less than a threshold limit  active endpoints with affected paths length greater than the threshold limit

Robust Low Power VLSI Proposed ATPG Methodology 13 Ahmed, Nisar, Mohammad Tehranipoor, and Vinay Jayaram. "Timing-based delay test for screening small delay defects." In Proceedings of the 43rd annual Design Automation Conference, pp ACM, 2006.

Robust Low Power VLSI Proposed ATPG Methodology 14 Ahmed, Nisar, Mohammad Tehranipoor, and Vinay Jayaram. "Timing-based delay test for screening small delay defects." In Proceedings of the 43rd annual Design Automation Conference, pp ACM, 2006.

Robust Low Power VLSI Proposed ATPG Methodology 15 Ahmed, Nisar, Mohammad Tehranipoor, and Vinay Jayaram. "Timing-based delay test for screening small delay defects." In Proceedings of the 43rd annual Design Automation Conference, pp ACM, 2006.

Robust Low Power VLSI Results 16 Ahmed, Nisar, Mohammad Tehranipoor, and Vinay Jayaram. "Timing-based delay test for screening small delay defects." In Proceedings of the 43rd annual Design Automation Conference, pp ACM,  The proposed approach generates more patterns

Robust Low Power VLSI Results 17 Ahmed, Nisar, Mohammad Tehranipoor, and Vinay Jayaram. "Timing-based delay test for screening small delay defects." In Proceedings of the 43rd annual Design Automation Conference, pp ACM, 2006.

Robust Low Power VLSI Questions  What is the overhead of using their ATPG technique?  What challenges we probably will have if using their approach?  The authors mentioned their approach also applies to short paths. Is it worth to apply this to short paths after defects on long paths are already found? 18

Robust Low Power VLSI Papers  [1] Ahmed, Nisar, Mohammad Tehranipoor, and Vinay Jayaram. "Timing-based delay test for screening small delay defects." In Proceedings of the 43rd annual Design Automation Conference, pp ACM,  [2] K. Cheng, “Transition Fault Testing for Sequential Circuits,” IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, vol. 12, no. 12, pp , Dec  [3] T. M. Mak, A. Krstic, K. Cheng and L. Wang, “New challenges in delay testing of nanometer, multigigahertz designs,” IEEE Design & Test of Computers, pp , May-Jun  [4] B. Benware, C. Schuermyer, N. Tamarapalli, Kun-Han Tsai,S. Ranganathan, R. Madge, J. Rajski and P. Krishnamurthy,“Impact of multiple-detect test patterns on product quality,” in Proc. Int. Test Conf. (ITC’03), pp ,  [5] B. Kruseman, A. K. Majhi, G. Gronthoud and S. Eichenberger, “On hazard-free patterns for fine-delay fault testing,” in Proc. Int. Test Conf. (ITC’04), pp ,

Robust Low Power VLSI Paper Map 19 [1] Small Delay Defects Detection for Long Path [2] Transition Fault Testing [4] Multiple-Detect Concept cvcv [3] General Delay Testing in Nano-Scale [5] Small Delay Detect for Short Paths cvcv