Sidewall Image Transfer Technology Bobby Schneider

Outline What is Sidewall Image Transfer (SIT)? Methods A, B, C What has this been used for? – μm² SRAM cell SIT & the future

What is Sidewall Image Transfer? A processing method – SIT uses optical lithography to obtain sub-resolution linewidths! (e.g. 20 nm) Will be used in next-gen CMOS processing – 22 nm and beyond – Useful for making finFETs

a)Pattern photoresist (PR) b)Deposit a thin conformal film (e.g. 30 nm) c)Do a short anisotropic etch d)Strip the PR Sidewall Image Transfer Method A (The easiest method) Microlithography: science and technology By Kazuaki Suzuki, Bruce W. Smith SIT forms closed loops Not flat

SIT Design Consideration Uses two masks – Collar (makes closed loops) – Trim (to define lines) Collar maskResultTrim mask PitchLine-width

Sidewall Image Transfer Method B (Furukawa et al.) Width defined by HF etch duration (e.g. 20 nm) Si SubstrateSiO 2 Poly-Si Si 3 N 4 Tungsten (W)

Sidewall Image Transfer Method B (Furukawa et al.) Width defined by HF etch duration (e.g. 20 nm) Si SubstrateSiO 2 Poly-Si Si 3 N 4 Tungsten (W)

Sidewall Image Transfer Method B (Furukawa et al.) Si SubstrateSiO 2 Poly-Si Si 3 N 4 Tungsten (W)

SIT Method B Result (Furukawa et al.) Si SubstrateSiO 2 Poly-Si Si 3 N 4 Tungsten (W) Small pitch (40 nm pitch possible) Narrow line-width (12 nm width possible) No feet

Sidewall Image Transfer – Method C (Furukawa et al.) Si SubstrateSiO 2 Poly-Si Si 3 N 4 Photoresist (PR)Germanium (Ge)

Sidewall Image Transfer – Method C (Furukawa et al.) Si SubstrateSiO 2 Poly-Si Si 3 N 4 Photoresist (PR)Germanium (Ge)

Sidewall Image Transfer – Method C (Furukawa et al.) Si SubstrateSiO 2 Poly-Si Si 3 N 4 Photoresist (PR)Germanium (Ge)

SIT Method C Result (Furukawa et al.) Small pitch (40 nm pitch possible) Narrow line-width (12 nm width possible) Si SubstrateSiO 2 Poly-Si Si 3 N 4 Photoresist (PR)Germanium (Ge) No feet

How has SIT been used? “… the smallest FinFET SRAM cell size of μm² reported to date using optical lithography.” (Basker et al. 2010)

How has SIT been used? (Ctd.)

FinFET Performance

SIT & The Future “CMOS Transitions to 22 and 15 nm” – David Lammers, News Editor -- Semiconductor International, 1/1/2010 “Scott Thompson, a former Intel technology manager who now teaches at the University of Florida at Gainesville, believes Intel will adopt a tri- gate structure at some point, while the rest of the industry will shy away from the manufacturing challenges of finFETs.” “I believe most people in the industry would agree that finFET processing is more difficult. Lithography is a huge challenge, though people can overcome that with sidewall image transfer.” -Bruce Doris, manager of advanced device integration at IBM's Albany, N.Y., R&D center

Takeaways… Things to remember: – Sidewall image transfer (SIT) uses optical lithography to achieve very narrow linewidths – 12 nm linewidths achieved, 40 nm pitch – 2 masks: Collar & Trim – Linewidth controlled by etch distance of sidewall – SIT will possibly be used at the 15 nm node of CMOS by Intel

Thank you! – That’s all.