Senior Capstone Project GPS Signal Simulator May 2, 2006 Benjamin Herreid Anthony Hoehne Advisor: Dr. In Soo Ahn Sponsored By:

Outline Project Description Block Diagram Software Hardware System Inputs GUI Application Software/Hardware Interface Hardware FPGA RF side Results and Future Work

Project Summary Global Positioning System (GPS) Satellite based navigation system Guaranteed worldwide coverage Solve problem backwards Generate the simulated GPS signals for up to 4 visible satellites (channels) Use generated signals to drive a commercial receiver

Project Application Model a scenario that uses GPS signals Useful in developing a GPS receiver Much cheaper than physical testing Airplanes Spacecraft Tests that are impossible in real life Repeatability High-dynamics

Equipment PC – Windows XP, Parallel Port FPGA – Altera Cyclone Altera UP3 Development Board D/A Converter, OpAmp MAX5184, 10 bits LM311 Mixer and Oscillator RF Signal Generator Commercial Receiver Ashtech G8

Block Diagram Input data: GUI, Files Data from PC to FPGA SV Number Input data: GUI, Files Data from PC to FPGA 2kHz, Digital GPS Signal to Mixer Analog, IF = 2.046 MHz Sampling Rate = 8.184 MHz GPS Signal to Receiver Analog, L1 = 1.57542 GHz

PC Data Path

Trajectory File Proprietary Duration of Jerk 4 axes: Roll, Pitch (Elevation), Yaw (Heading), Thrust Roll Pitch Yaw

Initial Conditions 3rd Derivative Requires initial conditions for lower order parameters Acceleration: 0 Velocity: 0 Attitude: 0 (level, due North) Position: Specified by User

Almanac and Antenna Files Almanac File Standard - Rinex 2 Ephemeris Data Antenna File Proprietary Antenna Gain Azimuth, Elevation

Phase and Visibility Files Phase File Phase (distance) to each satellite in radians At fixed frequency, wavelength is constant so phase and distance are interchangeable (fλ=c) Visibility File Azimuth and Elevation of each satellite Signal Power from each satellite

Application Screenshot

Application Screenshot

PC to FPGA Communication 4 Channels SVN: 5 bits Amplitude: 7 bits Roll Flags: 2 bits Phase: 18 bits Total: 32 bits 4 bytes 7 6 5 4 3 2 1 0 2 1 0 Byte 1 3 2 1 0 1 0 Byte 2 Byte 3 Byte 4 Minimum Communication Rate: 4 bytes/channel x 4 channels x 2kHz Update Rate = 32kHz

Outline Project Description Block Diagram Software Hardware System Inputs GUI Application Software/Hardware Interface Hardware FPGA RF side Results and Future Work

FPGA Calculations

Interpolation Wrapping

Signal Spectrum

RF Subsystem D/A converter LM311 OpAmp Mixer and signal generator MAX5184 – 10 bit 40MHz, Differential voltage output LM311 OpAmp Conversion to single-ended signal Mixer and signal generator Attenuation -130dBm required for receiver 90dB attenuation needed (-40dBm at D/A)

Results PC FPGA RF GUI finished Individual programs run Data ready for packing FPGA Single channel nearly completed Problems with Quartus II RF D/A – Not completed Mixer – Experimented, not implemented

Simulations Interpolation and lookup table indexing

Simulations C/A code generation for SV #1 / Ch 1

Future Work Establish Communication Add navigation data Additional features Ionosphere and troposphere effects Multipath Additional channels (multiple FPGA’s) Instrument panel in GUI

Questions?

RF Experimenting