1 Physical Hierarchy Generation with Routing Congestion Control Chin-Chih Chang *, Jason Cong *, Zhigang (David) Pan +, and Xin Yuan * * UCLA Computer Science Department + IBM T.J. Watson Research Center This paper is supported in part by SRC, an IBM Faculty Partnership Award, a grant from Intel, and a grant from Fujitsu under the California MICRO program

2 Overview n Motivation and problem formulation for physical hierarchy generation n Algorithm and contributions u Multilevel coarse placement framework u Hierarchical area density control u Fast incremental global routing n Experimental results n Conclusions

3 Challenges in Deep Sub-micron VLSI Designs n Performance Problems – need to optimize the dominating factor, i.e. interconnect delays u See interconnects as early as possible u Optimize interconnects in almost all design stages n Design convergence problems – need to eliminate mismatches between early estimations and final layouts u Accurate estimation/optimization of interconnect delay in early design stages u Consider interconnect routability in early design stages u Consider crosstalk noise impacts in early design stages n Require accurate global interconnect estimation/optimization in early design stages

4 Physical Hierarchy Generation Problem Formulation Hard IPSoft module Same color for modules of the same logic hierarchy Logical Hierarchy Assign modules to physical hierarchy Defines global interconnects Optimization objectives of this work: wire length minimization routing congestion minimization Physical Hierarchy = Placement bins + module locations Other objectives could also be used (not a complete list): performance, noise, power, etc.

5 Discussions on Previous Work on Placement with Routability Considerations n Modeling methods: u Weighted BBOX [Cheng ICCAD’94], weighted BBOX with congestion region expansion: [Yang ICCAD’01] u Reconstruction of Steiner tree on each move: [Tsay Intl. Conf. Asic’92] n Optimization methods: u Recursive partition placement with pre-computed Steiner tree [Mayrhofer ICCAD’90] u Cell padding or region growing/shrinking: [Hou ASPDAC’01], [Sadakane CICC’97], [Parakh DAC’98], [Brenner ISPD’02], [Yang ISPD’02] n Most accurate routing estimation from global routing itself. Need to find tradeoff between accuracy and run time

6 Algorithm Overview: V-shape Multi- Level Coarse Placement Coarsening by clustering Refinement by placement Initial Placement n Congestion driven at the finest few placement levels n Fast global routing for congestion estimation

7 Algorithm Overview - Clustering Finest cluster levelCoarsest cluster level n Clustering: group clusters (or cells) together n Usually under certain area constraints n Clustering criteria: connectivity driven, performance driven, etc.

8 Algorithm Overview - Refinement by Placement Initial Coarsest Level Placement Declustering Placement Declustering Placement Final coarse placement solution n Use the same grid structure in each level of placement n Variable cluster size (may bigger than a bin): handled by hierarchical area density control n Use fast incremental routing for congestion estimation

9 Area Density Problems in Multi-level Coarse Placement n Traditional area density control: n Cell area in each bin < bin area utilization with a small percentage of overflow n Does not work when cluster sizes may have significant variations and may be bigger than a bin n How about use different grid sizes for different levels of clustering? n Hard to find fixed percentages that works n Significant placement cost jump when switch grid sizes

10 Hierarchical Area Density Control n Use the same grid structure for placement for all clustering levels n Impose hierarchy on bin structure for area density control n Each cluster move must satisfy the area constraints on each level in the bin hierarchy n Area constraint for moving a cell of size A n Allowed overflow on each level in the bin hierarchy = kA, k is a small constant (usually 1 or 2) n Work well in multi-level framework: n Area constraints gradually tightened during optimization

11 Fast Incremental A-tree Routing for Multi-pin Nets  Simple incremental A-tree  Recursively Quad-partition grids  Each pin recursively connects to lower left corner of each level of partition  For net with bounding box length B, at most 2 *log B edge updates for each pin move, except the root.  Each edge routed by LZ-router First Quadrant Root(source pin)

12 Fast LZ-routing for Two-pin Connections n Decide HVH or VHV: n Select the less congested layer n Binary search on V-stem (or H-stem) n Initial left region and right region to cover bounding box n Repeat n Query wire usage on both regions n Select region with less congestion n Wire usage query can be done in O(log grid_size) Left region Right region HVH VHV

13 Placement Cost Functions n Wire length driven: Summation of net bounding boxes of all nets n Congestion driven: u Wire usages estimated from the fast global router u Cost = Summation of square of wire usages in all bins u For fixed wire width F cost equivalent to summation of weighted wire length, weight on a bin = wire usage of the bin u For congestion driven run: only turns on congestion driven cost at the finest placement level W1W2 W3 Congestion cost = W1 2 + W2 2 + … + W9 2 W4W5 W6 W7W8 W9

14 Experimental Results on Wire Length Minimization n Multi-level simulated annealing coarse placement n Wire length comparison with GORDIAN-L: u Our engine only turns on wire length optimization u Legalized by DOMINO for wire length comparison Our multi-level engine performs well for big circuits 20k-50k test cases: avqlarge, avqsmall, ibm04, ibm07 50k-100k test cases: ibm09, ibm10 100k-210k test cases: ibm14, ibm15, ibm16, ibm17, ibm18

15 Experimental Results on Congestion Control BBOX WLRouted WLMax boundary congestion Total overflow CPU mPG11111 mPG-cg.rd mPG-cg Test cases: ibm01, ibm04, ibm07, ibm11, ibm13, ibm15 mPG: wire length driven mode mPG-cg: congestion driven at finest clustering level mPG-cg.rd: alternative congestion driven + wire length driven at fines clustering level

16 Conclusions n Multi-level simulated annealing coarse placement u Hierarchical area density control u Fast global routing estimation u Capable of wire length minimization with/without congestion minimization n Compare to GordianL, mPG generates comparable solution with 3-6 times speedup for test cases > 100K n Congestion driven mPG reduce estimated global routing overflows by 50%-80% with 6-19 times CPU time