EE365 Adv. Digital Circuit Design Clarkson University Lecture #13 Clock Skew & Synchronization

Topics Rissacher EE365Lect #13 More Serial Clock Skew Synchronization

Serial data systems (e.g., TPC) Rissacher EE365Lect #13

Serial data in the phone system (E-1) Mb/s links between phone switches and subscribers –partitioned into Kb/s channels Each channel gets a timeslot in a “frame” where it can send 8 bits every 125  sec. –8000 frames/sec Rissacher EE365Lect #13

Timeslot details count = 255 Rissacher EE365Lect #13

Parallel-to-serial conversion  256 LSBs are bit number Assert shift-register LOAD input during bit 7 Timeslot number can be decoded and used to select source of parallel data Serial data to destination count = 255 Rissacher EE365Lect #13

Serial-to- parallel conversion Synchronize destination’s counter to source’s Shift in serial data Detect that a complete byte has been received Holding register for complete byte Note: loads 0…0 Rissacher EE365Lect #13

Destination timing Serial-in, parallel-out shift register outputs Holding-register outputs Grab complete byte when available Rissacher EE365Lect #13

Serial communication on ONE wire Serial communication requires three signals: CLOCK, SYNC, and DATA. Yet only one “wire” is used. How? One solution: Manchester code. Or use a phase-locked loop (analog circuit) to extract clock from the data: Rissacher EE365Lect #13

Still a couple of problems Framing -- SYNC signal –Solution: Use a unique data pattern for SYNC PLL clock recovery -- what if too many zeroes are transmitted? PLL can’t stay in sync. –Solution: Use a code that guarantees a minimum number of ones –Phone system: Map > (creating slight voice distortion) Gigabit Ethernet: Uses 8B10B code, solving both problems –Map each byte into 8 bits –Use only a “good” subset of 2 10 code words –Use another code word for synchronization Rissacher EE365Lect #13

Synchronous System Structure Everything is clocked by the same, common clock Rissacher EE365Lect #13

Typical synchronous-system timing Outputs have one complete clock period to propagate to inputs. Must take into account flip-flop setup times at next clock period. Rissacher EE365Lect #13

Clock Skew –Clock signal may not reach all flip-flops simultaneously. –Output changes of flip-flops receiving “early” clock may reach D inputs of flip-flops with “late” clock too soon. Reasons for slowness: (a) wiring delays (b) capacitance (c) incorrect design Rissacher EE365Lect #13

Clock-skew calculation t ffpd(min) + t comb(min)  t hold  t skew(max) > 0 First two terms are minimum time after clock edge that a D input changes Hold time is earliest time that the input may change Clock skew subtracts from the available hold-time margin Compensating for clock skew: –Longer flip-flop propagation delay –Explicit combinational delays –Shorter (even negative) flip-flop hold times Rissacher EE365Lect #13

In-Class Practice Problem Rissacher EE365Lect #13 t ffpd(min) = 5 ns t comb(min) = 20 ns t hold = 20 ns t skew(max) = 10 ns Comb Logic (Excitation Eqns) CLK Delay Calculate whether clock-skew is an issue for the indicated Flip-Flop

In-Class Practice Problem Rissacher EE365Lect #13 t ffpd(min) = 5 ns t comb(min) = 20 ns t hold = 20 ns t skew(max) = 10 ns t ffpd(min) + t comb(min)  t hold  t skew(max) = -5 ns Calculate whether clock-skew is an issue for the indicated Flip-Flop

In-Class Practice Problem Rissacher EE365Lect #13 t ffpd(min) = 5 ns t comb(min) = 20 ns t hold = 20 ns t skew(max) = 10 ns Comb Logic (Excitation Eqns) CLK Delay Now add a delay to the circuit to fix the issue.

In-Class Practice Problem Rissacher EE365Lect #13 t ffpd(min) = 5 ns t comb(min) = 20 ns t hold = 20 ns t skew(max) = 10 ns Comb Logic (Excitation Eqns) CLK Delay > 5 ns

Example of bad clock distribution Rissacher EE365Lect #13

Clock distribution in ASICs This is what a typical ASIC router will do if you don’t lay out the clock by hand. Rissacher EE365Lect #13

“Clock-tree” solution Often laid out by hand Wide,fast metal (low R ==> fast RC time constant) Rissacher EE365Lect #13

Gating the clock Definitely a no-no –Glitches possible if control signal (CLKEN) is generated by the same clock –Excessive clock skew in any case. Rissacher EE365Lect #13

If you really must gate the clock... Rissacher EE365Lect #13

Asynchronous inputs Not all inputs are synchronized with the clock Examples: –Keystrokes –Sensor inputs –Data received from a network (transmitter has its own clock) Inputs must be synchronized with the system clock before being applied to a synchronous system. Rissacher EE365Lect #13

A simple synchronizer Rissacher EE365Lect #13

Only one synchronizer per input Rissacher EE365Lect #13

Even worse Combinational delays to the two synchronizers are likely to be different. Rissacher EE365Lect #13

The way to do it One synchronizer per input Carefully locate the synchronization points in a system. But still a problem -- the synchronizer output may become metastable when setup and hold time are not met. Rissacher EE365Lect #13

Recommended synchronizer design Hope that FF1 settles down before “META” is sampled. –In this case, “SYNCIN” is valid for almost a full clock period. –Can calculate the probability of “synchronizer failure” (FF1 still metastable when META sampled) Rissacher EE365Lect #13

Metastability decision window Rissacher EE365Lect #13

Metastability resolution time Rissacher EE365Lect #13

Flip-flop metastable behavior Probability of flip-flop output being in the metastable state is an exponentially decreasing function of t r (time since clock edge, a.k.a. “resolution time”). Stated another way, MTBF(t r ) = exp(t r /  ) / [T 0 f a], where  and T 0 are parameters for a particular flip-flop, f is the clock frequency, and a is the number of asynchronous transitions / sec Rissacher EE365Lect #13

Typical flip-flop metastability parameters exp(t r /  ) ________ [T 0 f a] MTBF = MTBF = 1000 yrs. F = 25 MHz a = 100 KHz t r = ? Rissacher EE365Lect #13

Is 1000 years enough? If MTBF = 1000 years and you ship 52,000 copies of the product, then some system experiences a mysterious failure every week. Real-world MTBFs must be much higher. How to get better MTBFs? –Use faster flip-flops But clock speeds keep getting faster, thwarting this approach. –Wait for multiple clock ticks to get a longer metastabilty resolution time Waiting longer usually doesn’t hurt performance …unless there is a critical “round-trip” handshake. Rissacher EE365Lect #13

Multiple-cycle synchronizer Clock-skew problem Rissacher EE365Lect #13

De-skewed multiple-cycle synchronizer Necessary in really high-speed systems DSYNCIN is valid for almost an entire clock period. Rissacher EE365Lect #13

Next time CPLDs FPGAs Rissacher EE365Lect #13