Digital Digital: Chapter 8. Sequential Logic Design Practices 1 Chapter 8. Sequential Logic Design Practices

Digital Digital: Chapter 8. Sequential Logic Design Practices 2 State-machine descriptions –Word descriptions –State tables –state diagrams –Transition lists –ABEL programs –VHDL programs Timing diagrams and specifications –A detailed timing diagram Timing margin –Indicates how much “worse than worst case” the individual components of a circuit can be without causing the circuit to fail. 8.1 Sequential-Circuit Documentation Standards

Digital Digital: Chapter 8. Sequential Logic Design Practices 3 Setup time margin t setup -t clk -t ffpd(max) - t comb(max) Hold time margin t ffpd(min) + t comb(min) -t hold For proper circuit operation we must have t setup -t clk -t ffpd(max) - t comb(max) > 0, and t ffpd(min) + t comb(min) -t hold > 0 Functional timing of a synchronous circuit (Fig. 8-2) Propagation delays of CMOS devices (Table 8.1)

Digital Digital: Chapter 8. Sequential Logic Design Practices Latches and Flip-Flops SSI latches and flip-flops (Fig. 8-3) Simple application of a latch –Switch debouncer (Fig. 8-4, Fig. 8-5, Fig. 8-6) Multibit registers and latches –Register: a collection of two or more flip-flops with a common clock input. –74x175 (Fig. 8-8), 74x174 (Fig. 8-9) –74x374 8-bit register and 74x273 (Fig. 8-10, Fig. 8-12) –74x373 8-bit latch (Fig. 8-11) –74x377 8-bit register with gated clock (Fig. 8-13) Registers and latches in ABELs and PLDs Registers and latches in VHDL

Digital Digital: Chapter 8. Sequential Logic Design Practices Counters Counter –Any clocked sequential circuit whose state diagram contains a single cycle. (Fig. 8-26) Modulus of a counter –is the number of states in the cycle. Modulo-m counter (divide-by-m counter) –A counter with m states n-bit binary counter –A counter has n flip-flops and has 2 n states, which are visited in the sequence 0, 1, 2, …, 2 n -1, 0, 1, …. Ripple counter (Fig. 8-27) –The quickest time when the most significant bit change is nt TQ

Digital Digital: Chapter 8. Sequential Logic Design Practices 6 Synchronous counter –A synchronous counter connects all of its flip-flops clock inputs to the same common CLK signal. (Fig. 8-28) –All flip-flop will change their outputs after only t TQ. –Synchronous serial counter (Fig. 8-28) The minimal time period that two successive clock ticks can be applied is t TQ +3t AND2 –Synchronous parallel counter (Fig. 8-29) The minimal time period that two successive clock ticks can be applied is t TQ +t AND4 MSI counters and applications –74x163 counter, Fig for logic symbol, Table 8-11 for state table, and Fig for logic diagram. –A free running 74x163 counter (Fig. 8-32), Fig for waveform.

Digital Digital: Chapter 8. Sequential Logic Design Practices 7 –Waveform for a free-running divide-by-10 counter (Fig. 8-34) –A modulo-11 counter (Fig. 8-35) –Another modulo-11 counter (Fig. 8-36) –A excess-3 decimal counter (Fig. 8-37), Fig for waveforms. –Cascading 74x163 counters (Fig. 8-39) –A modulo-193 counter (Fig. 8-40) Counters in ABEL and PLDs Counters in VHDL

Digital Digital: Chapter 8. Sequential Logic Design Practices Shift Registers A shift register is an n-bit register with a provisions for shifting its stored data by one bit position at each clock tick. – Serial-in, serial-out shift register (Fig. 8-46). –Serial-in, parallel-out shift register (Fig. 8-47) –Parallel-in, serial-out shift register (Fig. 8-48) –Parallel-in, parallel-out shift register (Fig. 8-49) MSI shift registers –74x164, 74x166, 74x194 (Fig. 8-50) –Logic diagram for 74x194 (Fig. 8-51) –Function table for 74x194 (Table 8-18) –8-bit universal shift register: 74x299 (Table 8-19, Fig. 8-52, 8- 53)

Digital Digital: Chapter 8. Sequential Logic Design Practices The World’s Biggest Shift-Register Application Digital telephony Central office Serial channel Multiplex ISDN (Integrated Services Digital Network)

Digital Digital: Chapter 8. Sequential Logic Design Practices Serial/Parallel Conversion Digital transmission system (Fig. 8-54) –Three signals accomplish transfer Clock –2.048 MHz, 32x bit bytes/per second –A frame contains 256 bits (equal to 125  s) –A time slot contains 8 bits Serial data Synchronization –SYNC: 1-bit wide to indicate the beginning of a frame Timing diagram for parallel-to-serial conversion (Fig. 8-55) Transmitter (Fig. 8-56) Receiver (Fig. 8-56) Timing diagram for serial-to-parallel conversion (Fig. 8-58)

Digital Digital: Chapter 8. Sequential Logic Design Practices ~8.5.6 Shift-Register Counter& Ring Counter A shift-register counter can be formed by combining a shift register with combinational logic such that its state diagram is cyclic. A ring counter is a shift-register counter that uses n-bit shift register to form a counter with n states. 4-bit ring counter (Fig. 8-59, 8-60) Problem with ring counter (Fig. 8-61) Self-correcting counter –Making all abnormal states transfer to normal states Self-correcting ring counter (Fig. 8-62, 8-63) Shift registers in ABEL and PLDS Shift registers in VHDL

Digital Digital: Chapter 8. Sequential Logic Design Practices Synchronous Design Methodology In a synchronous system, all flip-flops are clocked by the same common clock signal, and preset and clear inputs are not used, except for system initialization. A synchronous system structure (Fig. 8-79) Timing for a synchronous system (Fig. 8-80)

Digital Digital: Chapter 8. Sequential Logic Design Practices Impediments to Synchronous Design Clock skew –Definition The difference between arrival times of the clock at different memory devices –Example of clock skew (Fig. 8-85) –Influence of clock skew Reduce the setup and hold time margins. For proper operation t ffpd(min) + t comb(min) - t hold - t skew(max) > 0 t setup -t clk -t ffpd(max) - t comb(max) - t skew(max) > 0 –Reducing clock skew proper buffering the clock (Fig. 8-86) Better clock distribution (Fig. 8-87, 8-88)

Digital Digital: Chapter 8. Sequential Logic Design Practices 14 Gating clock –Why not to gate the clock (Fig. 8-89) –An acceptable way (Fig. 8-90) Asynchronous inputs –Why use the asynchronous inputs? –Problem with asynchronous inputs Meta-stable –Need synchronizers A simple one (Fig. 8-91)