CS 151 Digital Systems Design Lecture 21 Analyzing Sequential Circuits.

Slides:



Advertisements
Similar presentations
ENGIN112 L23: Finite State Machine Design Procedure October 27, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 23 Finite State Machine.
Advertisements

COE 202: Digital Logic Design Sequential Circuits Part 2
Clocked Synchronous State-machine Analysis
State-machine structure (Mealy)
State Machine Design Procedure
Analysis of Clocked Sequential Circuits
CPEN Digital System Design Chapter 5 Sequential Circuits Storage Elements and Sequential Circuit Analysis C. Gerousis © Logic and Computer Design.
Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 5 – Sequential Circuits Logic and Computer.
Circuits require memory to store intermediate data
Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 5 – Sequential Circuits Part 1 – Storage.
Sequential Circuit Analysis & Design Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals Dr. Aiman H. El-Maleh.
1 EE365 Sequential-circuit analysis. 2 Clocked synchronous seq. circuits A.k.a. “state machines” Use edge-triggered flip-flops All flip-flops are triggered.
1 Lecture 23 More Sequential Circuits Analysis. 2 Analysis of Combinational Vs. Sequential Circuits °Combinational : Boolean Equations Truth Table Output.
CS 140 Lecture 9 Professor CK Cheng 4/30/02. Part II. Sequential Network 1.Memory 2.Specification 3.Implementation S XY s i t+1 = g i (S t, x t )
CS 140 Lecture 8 Professor CK Cheng 4/26/02. Part II. Sequential Network 1.Memory SR, D, T, JK, 2.Specification S XY s i t+1 = g i (S t, X t )
1 CS 140 Lecture 9 Sequential Networks Professor CK Cheng CSE Dept. UC San Diego.
Sequential Circuits and Finite State Machines Prof. Sin-Min Lee
EECC341 - Shaaban #1 Lec # 14 Winter Clocked Synchronous State-Machines Such machines have the characteristics: –Sequential circuits designed.
Give qualifications of instructors: DAP
CS 151 Digital Systems Design Lecture 20 Sequential Circuits: Flip flops.
EE 4271 VLSI Design, Fall 2010 Sequential Circuits.
CS 140 Lecture 10 Professor CK Cheng 10/29/02. Part II. Sequential NetworkReminder 1.Flip flops 2.Specification 3.Implement Netlist  State Table  State.
Digital Logic Design Lecture 26. Announcements Exams will be returned on Thursday Final small quiz on Monday, 12/8. Final homework will be assigned Thursday,
ECE 301 – Digital Electronics Introduction to Sequential Logic Circuits (aka. Finite State Machines) and FSM Analysis (Lecture #17)
ECE 331 – Digital Systems Design Introduction to Sequential Logic Circuits (aka. Finite State Machines) and FSM Analysis (Lecture #19)
1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.
CS 140 Lecture 9 Professor CK Cheng 10/24/02. Sequential Network 1.Components F-Fs 2.Specification D Q Q’ CLK.
7.4 Clocked Synchronous State-Machine Analysis
Lecture 10 Topics: Sequential circuits Basic concepts Clocks
Lecture 8: Sequential Networks and Finite State Machines CSE 140: Components and Design Techniques for Digital Systems Fall 2014 CK Cheng Dept. of Computer.
SEQUENTIAL CIRCUITS Introduction
T Flip-Flop A T (toggle) flip-flop is a complementing flip-flop and can be obtained from a JK flip-flop when the two inputs are tied together. When T =
Circuit, State Diagram, State Table
Digital Logic Design Sequential circuits
Introduction to Sequential Circuit By : Pn Siti Nor Diana Ismail CHAPTER 5.
Introduction to Sequential Logic Design Finite State-Machine Design.
1 Lecture 22 Sequential Circuits Analysis. 2 Combinational vs. Sequential  Combinational Logic Circuit  Output is a function only of the present inputs.
Fall 2004EE 3563 Digital Systems Design EE3563 Chapter 7, 8, 10 Reading Assignments  7.1, 7.2, 7.3  8.1, ,   8.5.1, 8.5.2,
2017/4/24 1.
Lecture 9: Sequential Networks: Implementation CSE 140: Components and Design Techniques for Digital Systems Fall 2014 CK Cheng Dept. of Computer Science.
DLD Lecture 26 Finite State Machine Design Procedure.
ANALYSIS OF SEQUENTIAL CIRCUITS by Dr. Amin Danial Asham.
Sequential Circuit: Analysis BIL- 223 Logic Circuit Design Ege University Department of Computer Engineering.
Analysis and Synthesis of Synchronous Sequential Circuits A “synchronizing” pulse/edge signal (clock) controls the operation of the memory portion of the.
Sahar Mosleh PageCalifornia State University San Marcos 1 More on Flip Flop State Table and State Diagram.
ENG241 Digital Design Week #7 Sequential Circuits (Part B)
Introduction to Sequential Logic Design Finite State-Machine Analysis.
IKI b-Analysis of Sequential Logic Bobby Nazief Semester-I The materials on these slides are adopted from: CS231’s Lecture Notes at.
Sequential circuit analysis1 Sequential Circuit Analysis Last time we started talking about latches and flip-flops, which are basic one-bit memory units.
Chapter 6 Analysis of Sequential Systems Sequential Memory Feedback.
1 KU College of Engineering Elec 204: Digital Systems Design Lecture 13 Edge-Triggered FF Operation.
1 Clocked synchronous seq. circuits A.k.a. “state machines” Use edge-triggered flip-flops All flip-flops are triggered from the same master clock signal,
Lecture #17: Clocked Synchronous State-Machine Analysis
2018/5/2 EE 4271 VLSI Design, Fall 2016 Sequential Circuits.
Week #7 Sequential Circuits (Part B)
Sequential Networks and Finite State Machines
Introduction to Sequential Logic Design
ANALYSIS OF SEQUENTIAL CIRCUITS
Adapted by Dr. Adel Ammar
FIGURE 5.1 Block diagram of sequential circuit
DESIGN OF SEQUENTIAL CIRCUITS
Digital Design Lecture 9
2018/8/29 EE 4271 VLSI Design, Fall 2013 Sequential Circuits.
Asynchronous Inputs of a Flip-Flop
T Flip-Flop A T (toggle) flip-flop is a complementing flip-flop and can be obtained from a JK flip-flop when the two inputs are tied together. When T.
MTE 202, Summer 2016 Digital Circuits Dr.-Ing. Saleh Hussin
SYEN 3330 Digital Systems Chapter 6 – Part 3 SYEN 3330 Digital Systems.
Sequential Circuits UNIT- IV
CSE 140 Lecture 9 Sequential Networks
2019/9/26 EE 4271 VLSI Design, Fall 2012 Sequential Circuits.
Presentation transcript:

CS 151 Digital Systems Design Lecture 21 Analyzing Sequential Circuits

Overview °Understanding flip flop state: Stored values inside flip flops °Clocked sequential circuits: Contain flip flops °Representations of state: State equations State table State diagram °Finite state machines Mealy machine Moore machine

Flip Flop State °Behavior of clocked sequential circuit can be determined from inputs, outputs and FF state y(t) = x(t)Q 1 (t)Q 0 (t) Q 0 (t+1) = D 0 (t) = x(t)Q 1 (t) Q 1 (t+1) = D 1 (t) = x(t) + Q 0 (t) x Q1Q1 Q0Q0 D Q Q’ D Q y Q0Q0 Q1Q1 D0D0 D1D1 Clk

Output and State Equations °Next state dependent on previous state. State equations Output equation y(t) = x(t)Q 1 (t)Q 0 (t) Q 0 (t+1) = D 0 (t) = x(t)Q 1 (t) Q 1 (t+1) = D 1 (t) = x(t) + Q 0 (t) x Q1Q1 Q0Q0 D Q Q’ D Q y Q0Q0 Q1Q1 D0D0 D1D1 Clk

State Table °Sequence of outputs, inputs, and flip flop states enumerated in state table °Present state indicates current value of flip flops °Next state indicates state after next rising clock edge °Output is output value on current clock edge Present State Next State x=0 x= Q 1 (t) Q 0 (t) Q 1 (t+1) Q 0 (t+1) x=0 x=1 Output State Table

°All possible input combinations enumerated °All possible state combinations enumerated °Separate columns for each output value. °Sometimes easier to designate a symbol for each state. Present State Next State x=0 x=1 s 0 s s 2 s s 0 s s 2 s x=0 x=1 Output s0s1s2s3s0s1s2s3 Let: s 0 = 00 s 1 = 01 s 2 = 10 s 3 = 11

State Diagram °Circles indicate current state °Arrows point to next state °For x/y, x is input and y is output Present State Next State x=0 x= x=0 x=1 Output /00/0 1/01/0 0/00/0 1/01/0 0/00/0 0/00/0 11 1/11/1 1/01/0

State Diagram s1s1 s2s2 s0s0 0/0 1/0 0/0 1/0 0/0 s3s3 1/1 1/0 °Each state has two arrows leaving °One for x = 0 and one for x = 1 °Unlimited arrows can enter a state °Note use of state names in this example °Easier to identify

Flip Flop Input Equations D Q0 = xQ 1 D Q1 = x + Q 0 °Boolean expressions which indicate the input to the flip flops. Format implies type of flop used x Q1Q1 Q0Q0 D Q Q’ D Q y Q0Q0 Q1Q1 D0D0 D1D1 Clk

Analysis with D Flip-Flops °Identify flip flop input equations °Identify output equation Note: this example has no output

Mealy Machine Comb. Logic X(t) Q(t+1) Q(t) Y(t) clk present state present input next state Comb. Logic Output based on state and present input Flip Flops

Moore Machine Comb. Logic X(t) Q(t+1) Q(t) Y(t) clk present state present input next state Comb. Logic Output based on state only Flip Flops

Mealy versus Moore

State Diagram with One Input & One Mealy Output °Mano text focuses on Mealy machines °State transitions are shown as a function of inputs and current outputs. S1 S2 S3 S4 1/0 1/1 Input(s)/Output(s) shown in transition 0/0 e.g. 1 0/0

State Diagram with One Input & a Moore Output °Moore machine: outputs only depend on the current state °Outputs cannot change during a clock pulse if the input variables change °Moore Machines usually have more states. °No direct path from inputs to outputs °Can be more reliable

Clocked Synchronous State-machine Analysis – next class Given the circuit diagram of a state machine: 1Analyze the combinational logic to determine flip-flop input (excitation) equations: D i = F i (Q, inputs) The input to each flip-flop is based upon current state and circuit inputs. 2Substitute excitation equations into flip-flop characteristic equations, giving transition equations: Q i (t+1) = H i ( D i ) 3From the circuit, find output equations: Z = G (Q, inputs) The outputs are based upon the current state and possibly the inputs. 4Construct a state transition/output table from the transition and output equations: Similar to truth table. Present state on the left side. Outputs and next state for each input value on the right side. Provide meaningful names for the states in state table, if possible. 5Draw the state diagram which is the graphical representation of state table.

Summary °Flip flops contain state information °State can be represented in several forms: State equations State table State diagram °Possible to convert between these forms °Circuits with state can take on a finite set of values Finite state machine °Two types of “machines” Mealy machine Moore machine