Minimizing Clock Skew in FPGAs

Slides:

Advertisements

Similar presentations

1 A latch is a pair of cross-coupled inverters –They can be NAND or NOR gates as shown –Consider their behavior (each step is one gate delay in time) –From.

Advertisements

FPGA (Field Programmable Gate Array)

EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Chapter 5 Programmable.

Digital Integrated Circuits A Design Perspective

Digital Logic Circuits (Part 2) Computer Architecture Computer Architecture.

Graduate Computer Architecture I Lecture 16: FPGA Design.

1 Lecture 28 Timing Analysis. 2 Overview °Circuits do not respond instantaneously to input changes °Predictable delay in transferring inputs to outputs.

Lecture #34 Page 1 ECE 4110–5110 Digital System Design Lecture #34 Agenda 1.Timing 2.Clocking Techniques Announcements 1.n/a.

EE141 © Digital Integrated Circuits 2nd Timing Issues 1 Digital Integrated Circuits A Design Perspective Timing Issues Jan M. Rabaey Anantha Chandrakasan.

Synchronous Digital Design Methodology and Guidelines

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Dr. Shi Dept. of Electrical and Computer Engineering.

ENGIN112 L28: Timing Analysis November 7, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 28 Timing Analysis.

Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR.

02/02/20091 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.

Digital Design – Optimizations and Tradeoffs

Programmable logic and FPGA

1/31/20081 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.

Introduction to Field Programmable Gate Arrays (FPGAs) COE 203 Digital Logic Laboratory Dr. Aiman El-Maleh College of Computer Sciences and Engineering.

February 4, 2002 John Wawrzynek

Chapter #6: Sequential Logic Design 6.2 Timing Methodologies

CS 151 Digital Systems Design Lecture 28 Timing Analysis.

Computer performance.

Robust Low Power VLSI R obust L ow P ower VLSI Finding the Optimal Switch Box Topology for an FPGA Interconnect Seyi Ayorinde Pooja Paul Chaudhury.

CSET 4650 Field Programmable Logic Devices

EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Chapter 7 Programmable.

Introduction to Interconnection Networks. Introduction to Interconnection network Digital systems(DS) are pervasive in modern society. Digital computers.

Lecture 2: Field Programmable Gate Arrays September 13, 2004 ECE 697F Reconfigurable Computing Lecture 2 Field Programmable Gate Arrays.

Power Reduction for FPGA using Multiple Vdd/Vth

Coarse and Fine Grain Programmable Overlay Architectures for FPGAs

EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Chapter 4 Programmable.

L7: Pipelining and Parallel Processing VADA Lab..

Hardware Implementation of a Memetic Algorithm for VLSI Circuit Layout Stephen Coe MSc Engineering Candidate Advisors: Dr. Shawki Areibi Dr. Medhat Moussa.

J. Christiansen, CERN - EP/MIC

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR FPGA Fabric n Elements of an FPGA fabric –Logic element –Placement –Wiring –I/O.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Topics n FPGA fabric architecture concepts.

Optimal digital circuit design Mohammad Sharifkhani.

A Routing Approach to Reduce Glitches in Low Power FPGAs Quang Dinh, Deming Chen, Martin D. F. Wong Department of Electrical and Computer Engineering University.

Basic Sequential Components CT101 – Computing Systems Organization.

Lecture 13: Logic Emulation October 25, 2004 ECE 697F Reconfigurable Computing Lecture 13 Logic Emulation.

Topics Combinational network delay.

Development of Programmable Architecture for Base-Band Processing S. Leung, A. Postula, Univ. of Queensland, Australia A. Hemani, Royal Institute of Tech.,

Timing Analysis Section Delay Time Def: Time required for output signal Y to change due to change in input signal X Up to now, we have assumed.

Section 1  Quickly identify faulty components  Design new, efficient testing methodologies to offset the complexity of FPGA testing as compared to.

1 Interconnect/Via. 2 Delay of Devices and Interconnect.

June 2005Computer Architecture, Background and MotivationSlide 1 Part I Background and Motivation.

Introduction to Clock Tree Synthesis

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Moore’s Law n Gordon Moore: co-founder of Intel. n Predicted that number of transistors.

ADC – FIR Filter – DAC KEVIN COOLEY. Overview  Components  Schematic  Hardware Design Considerations  Digital Filters/FPGA Design Tools  Questions.

Interconnect/Via.

A High-Speed & High-Capacity Single-Chip Copper Crossbar John Damiano, Bruce Duewer, Alan Glaser, Toby Schaffer, John Wilson, and Paul Franzon North Carolina.

CDA 4253 FPGA System Design RTL Design Methodology 1 Hao Zheng Comp Sci & Eng USF.

Static Timing Analysis

Clocking System Design

EE 466/586 VLSI Design Partha Pande School of EECS Washington State University

CSCE 211: Digital Logic Design Chin-Tser Huang University of South Carolina.

EEL 5722 FPGA Design Fall 2003 Digit-Serial DSP Functions Part I.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Topics n FPGA fabric architecture concepts.

Introduction to Field Programmable Gate Arrays (FPGAs) EDL Spring 2016 Johns Hopkins University Electrical and Computer Engineering March 2, 2016.

Sequential Logic Design

CSE 140 – Discussion 7 Nima Mousavi.

Lecture 15 Sequential Circuit Design

Pipelining and Retiming 1

Architecture & Organization 1

Chapter 11 Sequential Circuits.

We will be studying the architecture of XC3000.

Architecture & Organization 1

ARM implementation the design is divided into a data path section that is described in register transfer level (RTL) notation control section that is viewed.

SYEN 3330 Digital Systems Chapter 7 – Part 1 SYEN 3330 Digital Systems.

Pipeline Principle A non-pipelined system of combination circuits (A, B, C) that computation requires total of 300 picoseconds. Comb. logic.

Programmable logic and FPGA

Presentation transcript:

Minimizing Clock Skew in FPGAs Matthew Hamelback 12/5/13

FPGA Field Programmable Gate Array IC designed to by configured by customer Uses logic gates and RAM blocks to implement digital computations Fast I/Os and bidirectional data buses Challenge to get correct timing

Solutions to Minimize Clock Skew Placement Clock Tree Architecture (H-Tree versus Comb) Selection of modules / logic blocks Registers Pipelining Wave pipelining Direction of new algorithms

Clock Tree Architecture Comb H-Tree Clock signal passed down the spine then spreads out through the branches Does not have equal length traces All trace lengths are equal Minimizes clock skew clock

Selection of Modules Each module or logic block has a resistance and load capacitance Spreading out modules balances the load capacitance and the clock skew is not majorly affected Equivalent RC circuit of trace with the clockpin connected or disconnected: Not connected Connected Clock skew unaffected Clock skew affected

Pipelining Increases operating frequency by dividing the combinational logic into stages Registers are used in between stages Takes advantage of parallel processing Max clock rate is limited to the longest path of a single stage versus all stages together

Wave Pipelining Maximum rate pipelining Logic propagation depends on difference between longest and shortest traces Shaded region – Unstable Unshaded region - Stable Goal is equalization of path delays and minimizes unstable periods Improves speed with less area and clock load Uses an enable (en) signal to opening of output latch only when in the stable region

New Direction of Algorithms for FPGAs Traditional placement algorithms: Minimize area Minimize total wire lengths Satisfy timing requirements New placement algorithms for FPGAs have primary objective of minimizing clock skew depending on selected logic modules

References 1. Clock Skew Minimization During FPGA Placement (Zhu, Wong) http://ieeexplore.ieee.org.www2.lib.ku.edu:2048/stamp/stamp.jsp?tp=&arnumber=602474 2. A Novel Online Clock Skew Scheme (Santhi) http://ieeexplore.ieee.org.www2.lib.ku.edu:2048/stamp/stamp.jsp?tp=&arnumber=5482689 3. Exploiting Clock Skew Scheduling for FPGA (Bae) http://ieeexplore.ieee.org.www2.lib.ku.edu:2048/stamp/stamp.jsp?tp=&arnumber=509090 4 4. DLL-Based Multi-FPGA systems clock (Cheng-chang) http://ieeexplore.ieee.org.www2.lib.ku.edu:2048/stamp/stamp.jsp?tp=&arnumber=5514852