SOC Design Lecture 6 HREQ and HGRANT. Kyungoh Park & Youpyo Hong, DGU Multi Master & Single Slave(MM & SS) Multiple masters cannot access the same slave.

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Presentation transcript:

SOC Design Lecture 6 HREQ and HGRANT

Kyungoh Park & Youpyo Hong, DGU Multi Master & Single Slave(MM & SS) Multiple masters cannot access the same slave together. So, there must be a way to arbitrate them.

Kyungoh Park & Youpyo Hong, DGU Arbiter & HREADY Arbiter decides which master takes the bus. HREQUEST#x is a signal from Master#x to arbiter to try to use the bus. HGRANT#x is a signal from arbiter to Master#x to allow the master to use the bus. HREADY is a signal from a slave to indicate the slave is ready for access.

Kyungoh Park & Youpyo Hong, DGU Arbiter Timing Is the Arbiter a combinational or sequential circuit? That is, HREQ and HGRANT occurs simultaneously or not. Remember that the arbiter outputs are HGRANT#x and Master Selection. Is Master Selection defined by AMBA?

Kyungoh Park & Youpyo Hong, DGU Arbiter Timing Consider the three cases. 1. Single master requests the bus. (No arbitration needed.) 2. Two masters request the bus simultaneously. (Comb. Arbiter sounds OK.) 3. One master requests the bus while another master is using the bus. (Arbiter should be aware of the current situation) Think about if a master needs any delay between Request and Grant. Does spec. define it? Think about also when the separation of phase is needed. If the calculation is complex, it means long critical path.

Kyungoh Park & Youpyo Hong, DGU Pipeline (= Cycle Separation)

Kyungoh Park & Youpyo Hong, DGU HW #3 Explain what is defined and what is not defined about the timing between HREQ and HGRANT signals by AMBA spec. If their timing is not defined, decide the timing by yourself and explain the reason.