Decimation Filter A Design Perspective Presented by: Sameh Assem Ibrahim

What is Decimation ? M x[n] y[m] Two types of sampling rate conversion - Interpolation when F’ > F or T’ < T (inserting L-1 equidistant zero-valued samples between two consecutive samples of x[n] ) - Decimation when F’ < F or T’ > T (keeping every M-th sample of x[n] and removing M-1 in-between samples to generate y[m]) Decimation factor M M = F’/F <1 A block diagram representation M x[n] y[m]

The Use of Decimation in ΣΔ ADC -1- Analog input Digital FS Analog Output FN ΣΔ loops Decimator 1 bit Multiple bits FS is the high sampling rate used in the ΣΔ modulator FN is the Nyquist Sampling Rate = 2 Fmax FS >> FN FS/FN = M

The Use of Decimation in ΣΔ ADC -2- Converts ΣΔ bits stream into PCM data of required resolution (16 bits in our case) Reduces the sampling rate to Nyquist rate. This helps in: * Preventing inefficient use of bandwidth * Reduced speed of operation in the following circuits Suppresses out of band noise

Can we just Decrease the Sampling Rate? -1- ω X(j ω) -2πFmax 0 2πFmax 2πFS 4πFS FS > 2 Fmax ω X(j ω) -2πFmax 0 2πFmax 2πFS 4πFS FS < 2 Fmax 6πFS 8πFS 10πFS 12πFS Aliasing

Can we just Decrease the Sampling Rate? -2- 2πFN 2πFS 4πFS ΣΔ (FS >> 2 Fmax) ω X(j ω) No Problem if FS is integer multiples of FN 4πFN 6πFN 2πFN 2πFS 4πFS ΣΔ (FS >> 2 Fmax) ω X(j ω) πFS Noise shaped by ΣΔ Really?? Problem

Can we just Decrease the Sampling Rate? -3- A decimation filter is needed Design of a decimator is the design of its decimation filter Decimation filter is a digital filter It must have zeros at the integer multiples of the new sampling rate The Block diagram including the filter y[n] h[n] x[n] M y[m]

Digital Filters Background The Z-transform Z-transform is the discrete time counterpart of the Laplace transform Used in the analysis of LTI systems Used in the study of stability of a filter Im{z} Unit circle Re{z}

Digital Filters Background Some Z-transform Properties Linearity Time shifting Scaling in the z-domain Time expansion Convolution First difference Accumulation

Digital Filters Background The Discrete Fourier Transform Discrete Fourier transform is the discrete time counterpart of the continuous time Fourier transform In z-domain: Put r=1: Used in estimating the frequency response of a filter

Digital Filters Background Signal Flow Graphs Basic Elements Operation Symbol Time domain Description Frequency domain Description Unit delay x[n] z-1 y[n] y[n]=x[n-1] M-sample delay x[n] z-M y[n] y[n]=x[n-M] Gain x[n] c y[n] y[n]=cx[n] Gain and delay x[n] cz-1 y[n] y[n]=cx[n-1] Sampling rate compressor x[n] y[m] y[m]=x[Mm] Sampling rate expander Input branch x[n] -- Output branch y[n] M L

Digital Filters Background Signal Flow Graphs Operations z-1 c1 c2 x[n] y[n] y[n]=x[n]+c2x[n-1]+c1y[n-1] x1[n] y[n]=x1[n]+x2[n]+x3[n] x2[n] x3[n] y1[n]=x[n] x[n] y2[n]=x[n] y3[n]=x[n]

Digital Filters Background Basic Elements Implementations Delay units are implemented as D-FFs Gain units are implemented as digital multipliers implemented in VHDL or through ALUs Coefficients to be multiplied with are either stored in a ROM or have a generating digital circuitry if they have an easily implemented function Adding branches can be done using VHDL adders or ALUs Accumulators and first difference

Digital Filters Background Signal Flow Commutation Two branch operations commute if the order of their cascade operation can be interchanged without affecting the input-to- output response of the cascaded system.

Digital Filters Background FIR vs. IIR Filters The impulse response is non- zero for N samples only The impulse response duration is infinite They don’t contain any poles in the z-domain Have both poles and zeros in the z-domain Have no continuous time counterpart Are easily derived from continuous time filters Linear phase can be easily achieved Linear phase can only be approximated Always stable Must be checked for stability Coefficients can be rounded to reasonable word lengths This will result in large quantization noise Higher order than IIR is always required IIR filters are generally very efficient Most Implemented ΣΔ ADCs use FIR implementation

Decimation Filter Realization Structures used can be classified into: Direct Form Structures Polyphase structures Structures with time varying coefficients Each of these can be implemented using FIR or IIR filters. The choice depends on the application used Structures 3 are particularly useful when considering conversion by factors of L/M (not our case) Structures 1 and 2 can both be used

FIR Direct Form Structures A direct implementation of the convolution equation In many applications the FIR filter is designed to have linear phase Consequently, the impulse response is symmetric

FIR Direct Form Structures for Decimators Multiplications and additions are done at the low sampling frequency

Polyphase FIR Structures for Decimators Savings of a factor of M in the storage requirements can be achieved by proper design of filters

Single Stage vs. Multiple Stages If M can be factored into the product Then Decimation can be done in stages M1 x[n] y[m] h[n] M2 FS FS/M1 FS/M1M2=FS/M No Advantage

Filter Design Procedure Most implemented ΣΔ ADCs use a two stages decimation filter 1st Stage A Comb (sinck) Filter 2nd Stage An FIR filter with symmetric coefficients The 2nd stage reduces sampling rate to the Nyquist frequency Provides the sharp filtering necessary to reduce the frequency aliasing effect Provides the passband response compensation for the droop introduced by the “comb-filter” Provides linear phase relationship The first stage is realized as a direct form structure Reduces the sampling rate to 1/16 FS Introduces zeros around multiples of the new sampling frequencies These frequencies would alias into the required band and thus increases noise

Design of the Comb Filter -1- A comb-filter of length M is an FIR filter with all M coefficients equal to one. The transfer function of a comb-filter is The filter is a simple accumulator which performs a moving average. Using the formula for a geometric sum

Design of the Comb Filter -2- This can be written as Using commutation M X[z] Y(z) M X[z] Y(z)

Design of the Comb Filter -3- The accumulation is done at the higher rate The differentiation is done at the lower rate 2 registers only are required regardless of M The filter should be properly scaled for unity gain. This can be done by dividing over M The two’s complement number system should be used to avoid overflowing M X[z] Y(z)

Design of the Comb Filter -4- The advantages of a comb filter are No multipliers are required No storage is required for filter coefficients Intermediate storage is reduced by integrating at the high sampling rate and differentiating at the low sampling rate, compared to the equivalent implementation using cascaded uniform FIR filters The structure of comb-filters is very “regular” Little external control or complicated local timing is required The same filter design can easily be used for a wide range of rate change factors, M, with the addition of a scaling circuit and minimal changes to the filter timing

Design of the Comb Filter -5- A single comb filter will not give enough stop band attenuation Cascaded comb filters can often meet requirements The frequency response of a properly scaled M stage comb filter can be written as M FS/M 4 cascaded comb filters

Design of the Comb Filter -6-

Design of the Second Filter Stage Better to be designed in two low pass filter stages Stage 1 for the compensation of the droop in the passband introduced by the comb filter Stage 2 gives the final decimation ratio and provides for the required attenuation in the stop band MATLAB filter design and analysis tool can be used Stage A LPF FIR (Compensator) Stage B LPF FIR

Design of the Compensator -1- Compensates the droop of the comb filter Decimates by 2 Fixed point filter response 21 taps Symmetric FIR Filter specifications: (FIR) - Stopband slope (60 dB) - 5th order Inverse sinc - Passband, stopband ripple

Design of the Compensator -2- Zoom in on passband Cascaded response Comb filter response Compensation filter response added

Design of the Compensator -3- zoomed constant

Design of the Compensator -4- Realized as polyphase structure

Design of the Last Filter Stage -1- Implemented as an FIR LPF Gives the final attenuation in the stopband required Fixed point filter response 63 taps Symmetric FIR

Design of the Last Filter Stage -2- Final frequency Response

Design of the Last Filter Stage -3- Realized as a polyphase filter

References R.E.Crochiere, L.R. Rabiner, “Multirate Digital Signal Processing”, Prentice-Hall, 1983 J.C.Candy, G.C.Temes, “Oversampling Delta-Sigma Data Converters, Theory, Design and Simulation”, IEEE Press, 1992 D.Orifino, “Designing Digital Radio Applications with Simulink®”, The MathWorks, 2002 “Principles of Sigma-Delta Modulation for Analog to Digital Converters”, Motorola