PlayStation2 as a General Purpose Computer (The Emotion Engine vs. general PC architectures)

Can the PlayStation2 compete with the PC as a general purpose computer? What’s the difference between the general PC architecture and the PlayStation2 architecture? What’s the difference between the general PC architecture and the PlayStation2 architecture? How do these differences affect the performance of the PlayStation2 on general applications like word processing and running clients? How do these differences affect the performance of the PlayStation2 on general applications like word processing and running clients?

SISD vs. SIMD SISD – Single Instruction stream Single Data stream SISD – Single Instruction stream Single Data stream Intel and AMD Processors Intel and AMD Processors SIMD – Single Instruction stream Multiple Data streams SIMD – Single Instruction stream Multiple Data streams PlayStation2 PlayStation2 Motorola's MPC7400 (the G4) Motorola's MPC7400 (the G4) Sun's MAJC Sun's MAJC

SISD Takes advantage of instruction-level parallelism Takes advantage of instruction-level parallelism Executes multiple instructions at once on the same data stream Executes multiple instructions at once on the same data stream Good performance depends on good cache performance Good performance depends on good cache performance Very high clock speed (execute as many instructions as you can as fast as possible) Very high clock speed (execute as many instructions as you can as fast as possible)

SIMD Takes advantage of data parallelism Takes advantage of data parallelism Executes the same instruction on large amounts of uniform data all at once Executes the same instruction on large amounts of uniform data all at once Good performance depends on efficiently packing data into uniform format Good performance depends on efficiently packing data into uniform format Slower clock speed Slower clock speed Very high throughput Very high throughput

SISD/SIMD

SIMD on the PlayStation2 The heart of the PlayStation2 is the Emotion Engine The heart of the PlayStation2 is the Emotion Engine Its main function is to calculate display lists and send them on to a Graphics Synthesizer which renders these lists into three dimensional objects Its main function is to calculate display lists and send them on to a Graphics Synthesizer which renders these lists into three dimensional objects

Calculating display lists basically involves vector calculations Calculating display lists basically involves vector calculations the kind of task a SIMD architecture is perfect for the kind of task a SIMD architecture is perfect for It requires a relatively small set of instructions operating on massive amounts of uniform data It requires a relatively small set of instructions operating on massive amounts of uniform data The most common operation is a tight loop iterating through sets of matrices The most common operation is a tight loop iterating through sets of matrices SIMD on the PlayStation2

SISD data caches tend to be large SISD data caches tend to be large Huge performance gains are achieved by reading in a big chunk of data and executing as many instructions as you can on it Huge performance gains are achieved by reading in a big chunk of data and executing as many instructions as you can on it This approach is terrible for SIMD architecture This approach is terrible for SIMD architecture Data is not referenced repeatedly Data is not referenced repeatedly Vector calculations are performed and then the next bit of data is read Vector calculations are performed and then the next bit of data is read Nothing is gained by storing old data in cache memory Nothing is gained by storing old data in cache memory Differences in cache implementation

12K µop 8-way set associative execution trace cache 12K µop 8-way set associative execution trace cache 8K 8-way set associative data cache 8K 8-way set associative data cache 256K or 512K 8-way set associative Level 2 cache 256K or 512K 8-way set associative Level 2 cache The exact size of the L1 instruction cache is not clearly documented (8-12K would be a reasonable assumption) The exact size of the L1 instruction cache is not clearly documented (8-12K would be a reasonable assumption) Cache specs for the Pentium 4 (SISD architecture)

16K 2-way set associative instruction cache 16K 2-way set associative instruction cache 8K 2-way set associative data cache 8K 2-way set associative data cache Two Vector Units (VU0 and VU1) each have a 16K instruction cache and 16K data cache Two Vector Units (VU0 and VU1) each have a 16K instruction cache and 16K data cache 16K SPRAM (Scratch Pad RAM - high speed memory shared by the processor and VU0 16K SPRAM (Scratch Pad RAM - high speed memory shared by the processor and VU0 Cache specs for Emotion Engine (SIMD architecture)

The PlayStation total cache size is smaller than the Pentium 4 by a factor of about 3 or 5 depending on the size of the Pentium L2 cache The PlayStation total cache size is smaller than the Pentium 4 by a factor of about 3 or 5 depending on the size of the Pentium L2 cache Also, the caches are divided up into much smaller units on the Emotion Engine Also, the caches are divided up into much smaller units on the Emotion Engine The big difference is the lack of a L2 cache in the Emotion Engine The big difference is the lack of a L2 cache in the Emotion Engine Cache Specs

Designed with massive bandwith to maximize throughput Designed with massive bandwith to maximize throughput Memory bus bandwith: 3.2 GB/s Memory bus bandwith: 3.2 GB/s 16-bit bus connects two 128 MB RDRAM memory banks to the 10-channel Direct Memory Access Controller (DMAC) 16-bit bus connects two 128 MB RDRAM memory banks to the 10-channel Direct Memory Access Controller (DMAC) DMAC allows up to 10 simultaneous data transfers on 128-bit and 64-bit buses DMAC allows up to 10 simultaneous data transfers on 128-bit and 64-bit buses Much higher throughput is achieved because the system can service more requests simultaneously Much higher throughput is achieved because the system can service more requests simultaneously Bandwith in the Emotion Engine

General Purpose SISD Architecture

Emotion Engine Architecture

Performance of the PlayStation2 In multi media applications In multi media applications Outperforms PC’s by far on tasks such as Outperforms PC’s by far on tasks such as mp3 encoding/decoding mp3 encoding/decoding mpeg encoding/decoding mpeg encoding/decoding graphics applications graphics applications In applications that have very little data parallelism (like word processing, , or internet browsing) In applications that have very little data parallelism (like word processing, , or internet browsing) Degenerates to a machine with very low clock rate and a terrible cache implementation Degenerates to a machine with very low clock rate and a terrible cache implementation Cannot possibly compete with modern PC’s Cannot possibly compete with modern PC’s

Can the PlayStation2 compete with general purpose CPU’s? Not currently Not currently The lack of a L2 cache makes it difficult to compete with SISD architectures on workloads with high data reuse The lack of a L2 cache makes it difficult to compete with SISD architectures on workloads with high data reuse Even if we focus entirely on multimedia applications Even if we focus entirely on multimedia applications Code would have to be re-written and re-compiled to take advantage of the Emotion Engine’s higher bandwith and vector processors Code would have to be re-written and re-compiled to take advantage of the Emotion Engine’s higher bandwith and vector processors Not enough memory Not enough memory Only supports a total of 32MB Only supports a total of 32MB Not enough permanent storage Not enough permanent storage Max storage capacity is 16MB (two 8MB memory cards) Max storage capacity is 16MB (two 8MB memory cards)

Some Necessary Improvements Several improvements are necessary if the PlayStation2 wants to compete with general purpose PC’s in the future. For example: Several improvements are necessary if the PlayStation2 wants to compete with general purpose PC’s in the future. For example: Memory hierarchy needs to be re-designed to accommodate SISD workloads Memory hierarchy needs to be re-designed to accommodate SISD workloads A level 2 cache and a trace execution cache would substantially improve performance A level 2 cache and a trace execution cache would substantially improve performance A more powerful core CPU is necessary A more powerful core CPU is necessary Wider issue Wider issue Improved branch predictor Improved branch predictor Programmers need to learn how to fully utilize the strengths of the Emotion Engine Architecture Programmers need to learn how to fully utilize the strengths of the Emotion Engine Architecture

The PlayStation2 will face tougher competition from PC architectures, like the G4, that are incorporating SIMD architectures into their design more aggressively The PlayStation2 will face tougher competition from PC architectures, like the G4, that are incorporating SIMD architectures into their design more aggressively It will be interesting to see how these new architectures compete with the PlayStation2 as 3D gaming systems It will be interesting to see how these new architectures compete with the PlayStation2 as 3D gaming systems In the Future

Jon “Hannibal” Stokes: Jon “Hannibal” Stokes: “Sound and Vision: A Technical Overview of the Emotion Engine” “Sound and Vision: A Technical Overview of the Emotion Engine” “The PlayStation2 vs. the PC: a System-level Comparison of Two 3D Platforms” “The PlayStation2 vs. the PC: a System-level Comparison of Two 3D Platforms” “3 1/2 SIMD Architectures “ “3 1/2 SIMD Architectures “ A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder Suzuoki, M.; Kutaragi, K.; et al Solid-State Circuits, IEEE Journal of, Volume: 34 Issue: 11, Nov Page(s): A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder Suzuoki, M.; Kutaragi, K.; et al Solid-State Circuits, IEEE Journal of, Volume: 34 Issue: 11, Nov Page(s): Vector unit architecture for emotion synthesis Kunimatsu, A.; Ide, N.; Sato, T.; Endo, Y.; Murakami, H.; Kamei, T.; Hirano, M.; Ishihara, F.; Tago, H.; Oka, M.; Ohba, A.; Yutaka, T.; Okada, T.; Suzuoki, M. IEEE Micro, Volume: 20 Issue: 2, March-April 2000 Page(s): Vector unit architecture for emotion synthesis Kunimatsu, A.; Ide, N.; Sato, T.; Endo, Y.; Murakami, H.; Kamei, T.; Hirano, M.; Ishihara, F.; Tago, H.; Oka, M.; Ohba, A.; Yutaka, T.; Okada, T.; Suzuoki, M. IEEE Micro, Volume: 20 Issue: 2, March-April 2000 Page(s): Designing and programming the emotion engine Oka, M.; Suzuoki, M. IEEE Micro, Volume: 19 Issue: 6, Nov.-Dec Page(s): Designing and programming the emotion engine Oka, M.; Suzuoki, M. IEEE Micro, Volume: 19 Issue: 6, Nov.-Dec Page(s): References