Pre-Director’s Review Findings & Recommendations RecommendationManagerStatus 9Update BOE for AlN boardsShawDone 10Establish the budget profile ASAPFlaugherDone.

Slides:



Advertisements
Similar presentations
02/06/2014James Leaver Slink Transition Card. 02/06/2014James Leaver Slink Transition Card Simple 6U board: –Provides interface between FED and Slink.
Advertisements

Ninth Lecture Hour 8:30 – 9:20 pm, Thursday, September 13
FQHC Look-Alike Change in Scope Module for Implementation of Electronic Information Systems August 5, 2010 Esther Paul, Public Health Analyst Anil Bommakanti,
Project Managers Update Roy Preece Particle Physics Department, STFC MICE Video Conference, 18 th September 2014.
Director’s Review July 25-27, 2006 T. Shaw1 DES Review DES Front End Electronics WBS 1.3 T. Shaw.
1 FTK Rear Transition Module Mircea Bogdan The University of Chicago November 11, 2014 Board Review.
L. Greiner 1HFT PXL LBNL F2F – March 14, 2012 STAR HFT The STAR-PXL sensor and electronics Progress report for F2F.
Planning & Scheduling Systems: From Design to Fabrication.
Cost, Schedule & Funding Closeout Jan Joint DOE/NSF CD2/3a Review 1 DOE/NSF Review of the Dark Energy Survey (DES) Project SC 6/7 Cost, Schedule.
Operating Committee Chair Report Scott Kinney, OC Chair March 25, 2015.
D.Websdale: RICH Meeting LHCb RICH group meeting: Wednesday 10th November, in B40-SS-C01 at 14:00. Agenda: 1. The Photodetector Panel’s proposition.
6 June 2002UK/HCAL common issues1 Paul Dauncey Imperial College Outline: UK commitments Trigger issues DAQ issues Readout electronics issues Many more.
Encryption Transaction with 3DES Team W2 Yervant Dermenjian (W21) Taewan Kim (W22) Evan Mengstab(W23) Xiaochun Zhu(W24) Objective: To implement a secure.
MINER A NuMI MINER A DAQ Review 12 September 2005 D. Casper UC Irvine WBS7: Electronics and Data Acquisition  Overview (this talk): D. Casper  Front-end.
MINER A NuMI MINER A DAQ Review 12 September 2005 D. Casper UC Irvine WBS 7.2 & 7.3: Data Acquisition D. Casper (UC Irvine)
Adjusting EPLC to your Project Colleen Robinson & Teresa Kinley Friday, February 6, 2009.
Uli Schäfer 1 Production and QA issues Design Modules have been designed, with schematic capture and layout, in Mainz (B.Bauss) Cadence design tools, data.
DES Collaboration Meeting, Chicago, December 11-13, 2006 T. Shaw1 DES Collaboration Meeting Front End Electronics Status T. Shaw, D. Huffman, M. Kozlovsky,
Asis AdvancedTCA Class What is a Backplane? A backplane is an electronic circuit board Sometimes called PCB (Printed Circuit Board) containing circuitry.
 A project is “a unique endeavor to produce a set of deliverables within clearly specified time, cost and quality constraints”
16 – 17 Jul 02Andrew Werner TRD Monitor Tube Readout Electronics: Shaping Peter Fisher, Bernard Wadsworth, Andrew Werner MIT 1.
Clock Board Test and Preliminary Acceptance Criteria Ciemat (Madrid), April 2009 Juan de Vicente, Javier Castilla, Gustavo Martínez.
1 E-911 Services Board Meeting General Business Meeting May 08,
Circuit board
CS 360 Lecture 3.  The software process is a structured set of activities required to develop a software system.  Fundamental Assumption:  Good software.
DES PMG Meeting, January 26, 2007 T. Shaw1 DES PMG Meeting Front End Electronics Status T. Shaw, D. Huffman, M. Kozlovsky, J. Olsen, W. Stuermer (FNAL)
Project Tracking. Questions... Why should we track a project that is underway? What aspects of a project need tracking?
1 The Impact of SAS 112 on Governmental Financial Statement Audits GAQC Member Conference Call January 4, 2007 Presented by Chuck Landes, CPA.
Executive Session Director’s CD-3b Review of the MicroBooNE Project January 18, 2012 Dean Hoffer.
James W. Bilbro JB Consulting International Huntsville, AL Using the Advancement Degree of Difficulty (AD 2 ) as an input to Risk Management Multi-dimensional.
OFFICE OF SCIENCE 2.3 Infrastructure and Installation Sims, Edwards 1.Does the conceptual design and planned implementation satisfy the performance specifications.
P. Shanahan June 13, Near Detector Electronics Status Status Production Issues Peter Shanahan FNAL MINOS Collaboration Meeting June 13, 2003.
HBD FEM Overall block diagram Individual building blocks Outlook ¼ detector build.
Hall D Online Meeting 28 March 2008 Fast Electronics R. Chris Cuevas Group Leader Jefferson Lab Experimental Nuclear Physics Division System Engineering.
21 March 2007 Controls 1 Hardware, Design and Standards Issues for ILC Controls Bob Downing.
Hall D Online Meeting 27 June 2008 Fast Electronics R. Chris Cuevas Jefferson Lab Experimental Nuclear Physics Division 12 GeV Trigger System Status Update.
Questions on IFPAC_SCHEMATIC. Signal Chain Preamplifier Compensation Capacitor should go to –Vs, not GND Where is resistor For compensation Network? Does.
3.1.1 Optics, Optical Corrector, Mechanical Systems M. Johns, C. Claver.
WMO WIGOS Project Office and Project Oversight Board ICG-WIGOS-3; Geneva, February WMO; WIGOS-PO.
PRODUCT IMPLEMENTATION Chapter 8 Tawatchai Iempairote September 23, 2041.
XLIX Engineering Design Firm © 2010 ENGR/ETGR Definition of Project 1 A project is “…a combination of human and non-human resources pulled together.
Mohammad Alipour Islamic Azad University, Ahvaz Branch.
Day 3 in the pmProject Management Project Management (PM) ADJUST.
PS VFE & PS/SPD FE Electronics Status and Plans 16 January 2008 LPC Clermont.
12/17/01 Ron Sidwell 1 Run2b Datapath 17 Dec Update Bill Reay, Ron Sidwell, Noel Stanton, Russell Taylor, Kansas State University.
©2008 TTW Where “Lean” principles are considered common sense and are implemented with a passion! Product Training Manufacturing Orders.
Strykowsky 1Project Review November 2, 2005 NCSX Project Review November 2, 2005 Cost and Schedule Ron Strykowsky.
DES Review CCD Focal Plane and Camera Roger Smith George Ricker.
Software Development Process CS 360 Lecture 3. Software Process The software process is a structured set of activities required to develop a software.
March 25, FVTX Monthly/Quarterly Report June, 2009 Technical Status, Cost & Schedule Melynda Brooks, LANL.
Brenna Flaugher, PMG, April 6, 2007 DECam Funding Need Profile (Dec 06) (then yr $, Overhead included) This gave a technically driven schedule resulting.
Project Control n How do I spot problems? n What do I do once I find them? n How do I stay on track? n What happened to my plan? n How do I stay flexible?
Robotic Locomotion XXXXXX Robot Group Name: Robot Name: Group Members:
CMGT 410 Course Tutorial For more course tutorials visit
Introduction to Project Management Project Closure and Transition Lecture a This material (Comp19_Unit11a) was developed by Johns Hopkins University, funded.
Develop Schedule is the Process of analyzing activity sequences, durations, resource requirements, and schedule constraints to create the project schedule.
Prof. Shrikant M. Harle.  The Project Life Cycle refers to a logical sequence of activities to accomplish the project’s goals or objectives.  Regardless.
Meeting CERN 28 Nov A.B.Lodge - RAL 1 ECAL CMS ECAL Mechatronics Task Force Meeting.. CMS ECAL Mechatronics Scheme Applicability to EE Meeting held.
Workplace Projects.
ISA 201 Intermediate Information Systems Acquisition
MicroTCA Common Platform For CMS Working Group
Local Oscillator Generation - Internal.
CMGT 410 Education for Service-- snaptutorial.com.
CMGT 410 AID Perfect Education/ cmgt410aid.com.
CMGT 410 HOMEWORK Perfect Education/ cmgt410homework.com.
CMGT 410 Teaching Effectively-- snaptutorial.com.
CMGT 410 HOMEWORK Education for Service-- cmgt410homework.com.
Electronics: Demod + 4Q FE
General Government & Policy Committee 2020 Levy and Budget Discussion
Presentation transcript:

Pre-Director’s Review Findings & Recommendations RecommendationManagerStatus 9Update BOE for AlN boardsShawDone 10Establish the budget profile ASAPFlaugherDone 11Create clear criteria for each stage of board development ShawIn progress 12Add design reviews for PCBs and other major components ShawWill be done 13Mitigate risk of circuit board damage from operator errors ShawWill have keying 14Scrub cost & schedule for consistency w/ supporting BOE documentation Thaler, Honscheid In progress 15Establish a fallback plan for labor shortfall in the SISPI area Thaler, Honscheid Done

T. Shaw November 16, Pre-Director’s Review Findings & Recommendations Finding –The documentation supporting the number of AlN boards to be fabricated, and the number of associated connectors to be procured, did not clearly indicate how the quantities were calculated. Comment –These quantities will need to be established prior to the CD-2/3a review. Recommendation #9 –Re-check these calculations and update the justification in the BOE. Tom Diehl will document our need to produce 200 boards in WBS section 1.2. I have updated the BOE to explain our board and connectors quantities based upon the board count.

T. Shaw November 16, Finding –The Front End Electronics subproject currently has 27 tasks within 4 weeks of the critical path. Comment –The critical path for the entire project is in flux due to the varying budget profile scenarios that are being considered. The members of the Front End Electronics subproject seemed surprised to learn that their tasks were now appearing near the critical path. Recommendation #10 –Establish the budget profile as soon as possible in order to take subsequent steps in the subprojects to reallocate resources and reduce the number of items near the critical path. I will work on the project file to reduce as many critical path items as feasible. Funding guidance has been received and the smoothing of the profile is in progress.

T. Shaw November 16, Finding –Recommendation 16 from the July, 2006 Director’s CD1 Review called for the subproject members to “Create a clear set of acceptance testing criteria for each stage of board development, which includes all components to be included. Design reviews between steps should include comparisons of results with these criteria and provide branch points such as eliminating design iterations or implementing fallback solutions.” Comment –This recommendation has not yet been implemented though the subproject members are considering how the criteria should be developed. Recommendation #11 –The subproject should follow through on implementing this recommendation. Our initial set of acceptance criteria for the DECam Monsoon boards has been to implement them into a CCD readout system, measure the noise and accept the board if the noise does not increase from our standard NOAO board group. After this initial test, we will measure the noise present on all clocks and biases through a Monsoon analog channel and establish a maximum acceptable noise threshhold.

T. Shaw November 16, Finding –The schedule called for a Multi-CCD Readout Review that was held on September 17, The next review that appears in the schedule for Front End Electronics is for a Production Electronics Review to be held on January 14, Comment –Design reviews help ensure that components being developed will meet their requirements. Recommendation #12 –Design reviews should be added for the printed circuit boards and for other major components being developed for the subproject. We will add these in the project file. Board reviews at the schematic and layout level are planned before manufacture of the next set of Monsoon Electronics.

T. Shaw November 16, Finding –Multiple circuit board designs are being implemented in the same form-factor, with the same style of backplane connectors, for main modules and transition boards. Comment –Circuit boards of the same form-factor, with the same connectors, can easily be inserted into a backplane slot that may not have a compatible companion module (main module or transition board) located in the same slot on the other side of the backplane. Recommendation #13 –The members of the subproject should determine whether damage can occur to circuit boards if a circuit board is inserted on the front of the backplane while a board that is not meant to be its companion is located on the back side of the backplane. If damage could result, steps should be taken to preclude this from happening. The production circuit boards may need to have a keying system implemented to prevent this from occurring at the telescope. Connectors J4 and J5 are for user-defined signals. Some incompatibilities exist between the usage of the pins of these connectors between the Clock and 12-Channel Board. We will provide keying of both the front and rear slots of the Monsoon readout crate.