A High-Speed Analog Min-Sum Iterative Decoder Saied Hemati, Amir H. Banihashemi, and Calvin Plett Carleton University, Ottawa, Canada.

Slides:

Advertisements

Similar presentations

T. Chalvatzis, University of Toronto - ESSCIRC Outline Motivation Decision Circuit Design Measurement Results Summary.

Advertisements

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter CMOS INVERTER.

Introduction to Digital Systems By Dr. John Abraham UT-Panam.

Houshmand Shirani-mehr 1,2, Tinoosh Mohsenin 3, Bevan Baas 1 1 VCL Computation Lab, ECE Department, UC Davis 2 Intel Corporation, Folsom, CA 3 University.

Predictably Low-Leakage ASIC Design using Leakage-immune Standard Cells Nikhil Jayakumar Sunil P. Khatri University of Colorado at Boulder.

Improving BER Performance of LDPC Codes Based on Intermediate Decoding Results Esa Alghonaim, M. Adnan Landolsi, Aiman El-Maleh King Fahd University of.

Pixel-level delta-sigma ADC with optimized area and power for vertically-integrated image sensors 1 Alireza Mahmoodi and Dileepan Joseph University of.

Design and Implementation a 8 bits Pipeline Analog to Digital Converter in The Technology 0.6 μm CMOS Process Eri Prasetyo.

Design Goal Design an Analog-to-Digital Conversion chip to meet demands of high quality voice applications such as: Digital Telephony, Digital Hearing.

1 A New Successive Approximation Architecture for Low-Power Low-Cost A/D Converter IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.38, NO.1, JANUARY 2003 Chi-sheng.

Cooperative Multiple Input Multiple Output Communication in Wireless Sensor Network: An Error Correcting Code approach using LDPC Code Goutham Kumar Kandukuri.

Statistical Full-Chip Leakage Analysis Considering Junction Tunneling Leakage Tao Li Zhiping Yu Institute of Microelectronics Tsinghua University.

By Hua Xiao and Amir H. Banihashemi

Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 4a1 Design for Testability Theory and Practice Lecture 4a: Simulation n What is simulation? n Design.

1 A Variation-tolerant Sub- threshold Design Approach Nikhil Jayakumar Sunil P. Khatri. Texas A&M University, College Station, TX.

Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response

EE 365 Introduction, Logic Circuits. Digital Logic Binary system -- 0 & 1, LOW & HIGH, negated and asserted. Basic building blocks -- AND, OR, NOT.

Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response Credits: David Harris Harvey Mudd College (Material taken/adapted from Harris’ lecture.

Code and Decoder Design of LDPC Codes for Gbps Systems Jeremy Thorpe Presented to: Microsoft Research

CMOS VLSIAnalog DesignSlide 1 CMOS VLSI Analog Design.

Microelectronic Circuits - Fourth Edition Sedra/Smith 0 Fig Switching times of the BJT in the simple inverter circuit of (a) when the input v 1 has.

The CMOS Inverter Slides adapted from:

Digital Integrated Circuits© Prentice Hall 1995 Inverter THE INVERTERS.

Rail-to-rail low-power high-slew-rate CMOS analogue buffer

1 EE 587 SoC Design & Test Partha Pande School of EECS Washington State University

Chihou Lee, Terry Yao, Alain Mangan, Kenneth Yau, Miles Copeland*, Sorin Voinigescu University of Toronto - Edward S. Rogers, Sr. Dept. of Electrical &

1 Delay Estimation Most digital designs have multiple data paths some of which are not critical. The critical path is defined as the path the offers the.

Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style Sumeer Goel, Ashok Kumar, and Magdy A. Bayoumi.

ENGG 6090 Topic Review1 How to reduce the power dissipation? Switching Activity Switched Capacitance Voltage Scaling.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. C H A P T E R 14 Advanced MOS and Bipolar Logic Circuits.

Wireless Mobile Communication and Transmission Lab. Theory and Technology of Error Control Coding Chapter 7 Low Density Parity Check Codes.

A 30-GS/sec Track and Hold Amplifier in 0.13-µm CMOS Technology

A Linear Regulator with Fast Digital Control for Biasing of Integrated DC-DC Converters A-VLSI class presentation Adopted from isscc Presented by: Siamak.

Assuring Application-level Correctness Against Soft Errors Jason Cong and Karthik Gururaj.

Filip Tavernier Karolina Poltorak Sandro Bonacini Paulo Moreira

Tinoosh Mohsenin and Bevan M. Baas VLSI Computation Lab, ECE Department University of California, Davis Split-Row: A Reduced Complexity, High Throughput.

Chapter 4 Logic Families.

Implementation of Infomax ICA Algorithm with Low-Power Analog CMOS Circuits Ki-Seok Cho and Soo-Young Lee Brain Science Research Center and Department.

Digital Logic Design Lecture # 9 University of Tehran.

IEEE Transactions on Circuits and Systems II: Express Briefs

Copyright 2002 An Analog Turbo Decoder for an (8,4) Product Code Matthew C. Valenti Assistant Professor Lane Dept. of Comp. Sci. & Elect. Eng. West Virginia.

DESIGN OF LOW POWER CURRENT-MODE FLASH ADC

A 1-V 2.4-GHz Low-Power Fractional-N Frequency Synthesizer with Sigma-Delta Modulator Controller 指導教授 : 林志明教授學生 : 黃世一 Shuenn-Yuh Lee; Chung-Han Cheng;

Bootstrapped Full-Swing CMOS Driver for Low Supply Voltage Operation Speaker ： Hsin-Chi Lai Advisor ︰ Zhi-Ming Lin National.

Jordi Madrenas Daniel Fernández Jordi Cosp Advanced Hardware Architectures Group Department of Electronic Engineering Universitat Politècnica de Catalunya.

Introduction to CMOS VLSI Design MOS devices: static and dynamic behavior.

New Power Saving Design Method for CMOS Flash ADC Institute of Computer, Communication and Control, Circuits and Systems, July 2004 IEEE 班級：積體碩一姓名：黃順和.

Integrated Smart Sensor Calibration Abstract Including at the sensor or sensor interface chip a programmable calibration facility, the calibration can.

1 1.3 V low close-in phase noise NMOS LC-VCO with parallel PMOS transistors Moon, H.; Nam, I.; Electronics Letters Volume 44, Issue 11, May Page(s):676.

Integrated VLSI Systems EEN4196 Title: 4-bit Parallel Full Adder.

Outline MSI Parts as a Decoder Multiplexer Three State Buffer MSI Parts as a Multiplexer Realization of Switching Functions Using Multiplexers.

Bi-CMOS Prakash B.

Multi-Split-Row Threshold Decoding Implementations for LDPC Codes

26 May 2004 A. Morgül – ISCAS’2004, Vancouver, Canada 1 A NEW LEVEL RESTORATION CIRCUIT FOR MULTI-VALUED LOGIC Avni MORGÜL and Turgay TEMEL Boğaziçi University.

A 20/30 Gbps CMOS Backplane Driver with Digital Pre-emphasis Paul Westergaard, Timothy Dickson, and Sorin Voinigescu University of Toronto Canada.

Low Power, High-Throughput AD Converters

Code Construction and FPGA Implementation of a Low-Error-Floor Multi-Rate Low-Density Parity-Check Code Decoder Lei Yang, Hui Liu, C.-J Richard Shi Transactions.

EE415 VLSI Design THE INVERTER [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

Outline Abstract Introduction Bluetooth receiver architecture

Seok-jae, Lee VLSI Signal Processing Lab. Korea University

Team LDPC, SoC Lab. CS Dept. National Taiwan University Codes and Decoding on General Graphs Speaker: Yi-hsin Jian.

Memory-efficient Turbo decoding architecture for LDPC codes

CMOS LOGIC STRUCTURE. 1.CMOS COMPLEMENTARY LOGIC CMOS is a tech. for constructing IC. CMOS referred to as Complementary Symmetry MOS(COS-MOS) Reason:

CMOS technology and CMOS Logic gate. Transistors in microprocessors.

Tinoosh Mohsenin 2, Houshmand Shirani-mehr 1, Bevan Baas 1 1 University of California, Davis 2 University of Maryland Baltimore County Low Power LDPC Decoder.

M. Atef, Hong Chen, and H. Zimmermann Vienna University of Technology

1 Aggregated Circulant Matrix Based LDPC Codes Yuming Zhu and Chaitali Chakrabarti Department of Electrical Engineering Arizona State.

Waseda University Low-Density Parity-Check Code: is an error correcting code which achieves information rates very close to the Shanon limit. Message-Passing.

An Improved Split-Row Threshold Decoding Algorithm for LDPC Codes

High Throughput LDPC Decoders Using a Multiple Split-Row Method

Presentation transcript:

A High-Speed Analog Min-Sum Iterative Decoder Saied Hemati, Amir H. Banihashemi, and Calvin Plett Carleton University, Ottawa, Canada

Outline  Introduction  Min-Sum Decoding Algorithm  Basic Modules and Circuits  Analog Min-Sum Decoder for a (32,8) Code  Measurement Results  Conclusion

Introduction Why analog?  Lower power/speed ratio  Lower noise generation  Lower area consumption  Better decoding performance (Hemati and Banihashemi, 2003) Previous Work: - Loeliger et al., Mondragon-Torres et al., Gaudet et al., Morez et al., Hemati et al., Winstead et al., Amat et al., 2004

 Other Approaches: - are b ased on belief propagation (BP) - have a d ifferential multiplier as the basic processing module - use the well-known Gilbert differential multiplier  Linearity of the Gilbert multiplier relies on the exponential behavior of bipolar (or quasi-bipolar weakly inverted CMOS) transistors.  Bipolar technology is expensive and weakly inverted CMOS transistors are slow.  Multiple-input modules are constructed by cascading two-input Gilbert multiplier modules.

 Our Approach: - is based on min-sum (MS) - does not require an estimate of the noise power - is more robust against quantization noise - is based on current mirrors - multiple-input modules can be directly implemented  There are simple modifications of MS that can perform very close to BP.

Min-sum Decoding Algorithm Basic operations in MS: mvmv V C

Basic Modules and Circuits Current buffers duplicate input current at the output with flipped sign

Variable Nodes Basic modules and circuits

Check Nodes Basic Modules and Circuits

An RTAS module, (a) current rectifier, (b) sign extractor Basic Modules and Circuits

(a) A current-mirror, (b) a current-mode 3- input max WTA. Basic Modules and Circuits (a) (b)

ASTR module Basic Modules and Circuits

Analog MS Decoder for a (32,8) Code Tanner graph of the code

Architecture of the implemented chip Analog MS Decoder for a (32,8) Code

Microphotograph of the fabricated chip Analog MS Decoder for a (32,8) Code

16/21 Measurement Results

TechnologyThroughput (Mb/s) Core (mm 2 ) Power (mW) Supply (V) TransistorsPower/ speed Code Lustenberger et al. 0.8µm BiCMOS BJT ( 940) p-MOS (650) 0.5 nJ/b (18,9,5) tailbiting Moerz et al. ‎ 0.25µm BiCMOS BJT ( 441) n-MOS (356) 0.06 nJ/b (16,8,3) tailbiting Gaudet et al.0.35µm CMOS (subthreshold) CMOS13.9 nJ/b Turbo Code (length 16) Winstead et al. ‎ 0.5µm CMOS (subthreshold) 2 (0.02) (0.016) 3.3CMOS0.5 nJ/b (0.8nJ/b) (8,4,4) Amat et al. ‎ 0.35µm CMOS (subthreshold) CMOS (26,000) 5.2 nJ/b Turbo Code (length 40) This work0.18µm CMOS CMOS (18,800) 0.2 nJ/b (32,8,10) Code

Conclusion  A modular methodology was proposed for designing CMOS analog MS iterative decoders.  The modules are based on current mirrors and therefore our approach can be used for implementing analog MS decoders in advanced bipolar and CMOS technologies.  A proof-of-concept analog MS decoder chip for a (32,8) regular LDPC code was fabricated and tested.  In low-SNR region, measurement results are close to the simulation results based on SR-MS algorithm.