Trends and Perspectives in deep-submicron IC design Bram Nauta MESA + Research Institute University of Twente, Enschede, The Netherlands University of Twente IWORID 2002

Outline IC Technology trends Analog v.s. digital circuits How to design circuits in new technologies? Conclusion

IC Technology Trends

P5 (Pentium) P6 (Pentium Pro) Pentium II Merced Doubling every 1.9 year 2.75 year Moore’s Law Number of Transistors 80x86 Processors

The ”ITRS" Roadmap Advanced research (materials, architecture,..) 180 (nm) Volume Production Integration/Pilot Basic steps/Modules Volume Production Basic steps/Modules Precompetitive today

Supply Voltage: V dd Why Low Voltage? Low power digital No breakdown today2012

Threshold voltage: V T Vdd Vss I on I off 0VTVT V DD large I on small I off ON OFF IdId V gs

V T dilemma Sub-threshold leakage becomes problem –low I dd during standby & test -> high V T –fast switching -> low V T dual V T Triple well (tune V T with voltage)

Transistor speed: cut-off frequency log [Id/Ig] Frequency f t is about the intrinsic transistor, not interconnect f t is a measure for the speed of (analog) circuits IdId IgIg 0 ftft

cut-off frequency

Example 30 nm Devices [Intel] 30 nm physical gate length 0.8 nm conventional SiO 2 (N) mass production in 2009

Interconnect: > 6 metal layers [Intel] Transistor gate length 70 nm Metal-1 width 180 nm

Analog v.s. Digital Circuits

Power dissipation for analog processing [Vittoz, ISCAS 1990] independent of technology

Power dissipation for digital processing 1 bit extra -> 6dB more S/N operations/sec ~ n 2. f sig depends on technology [Vittoz, ISCAS 1990]

Energy per transition: Vdd Idd C wire Etr=10pJ for 4um 5V CMOS Etr=1pJfor 1um 3V CMOS(1990) Etr=0.1pJ for 0.18um 1.8V CMOS(2000) ??????????(2020)

downscaling lowers digital dissipation Signal/Noise [dB] Power dissipation analog digital

IC Technology scaling Optimized for digital –digital = main chip area –minimize E tr –minimize cost per transistor Analog “has to live with this” –It cannot die

How to design circuits in new technologies?

Analog High voltage options for I/O & EEPROM –“old” transistors available in new technology Use the low V T –needed for digital speed anyway “non ideal” device behavior –gate leakage, non square law, –no real problem, better models needed Nominal V dd drops –no stacking

psrr, cmrr, noise Change analog circuits V dd =V gs + V ds

Analog matching of MOSFETS –becomes better for same W.L –new technology:  V T drops linear with V dd 1/f noise –tends to increase for minimum size MOS f N ftft ftft ftft

1/f noise Reduction: switched bias technique Constant Bias n-MOSFET V ON VTVT What about the Low-Frequency noise ? V OFF Switched Bias [Periodically switching the MOSFET “off”]

LF noise spectrum (constant DC gate bias) Expected noise spectrum of switched bias [6 dB below] (for 50% duty cycle) Noise Power(dB) Frequency(log scale) Switching frequency Measured noise spectrum of switched bias [>>6dB below] (for 50% duty cycle) 1/f noise Reduction: switched bias technique

analog RF: passives components Inductors –many metal layers + high ohmic substrate –high Q possible top view

analog RF: passives components C: use fringe caps! cross section view

Switched opamp technique V sig +V gs > V dd V sig V gs [Peluso, JSSC, july 97] V dd

Analog: strategy Exploit the speed: high frequencies –noise canceling –dynamic element matching –sigma delta AD high frequencies Use digital for analog –always digital on the chip –use this for: calibration, digital filtering

Digital transistor switching speed = no issue low voltage but still too high power !!! leakage -> dual V T –but which V T where? how to manage complexity? –100M transistors interconnect is speed bottleneck

interconnect 1980 substrate

interconnect 1995 substrate

interconnect 2005 substrate

Digital / interconnect bottleneck = wires –repeaters, synchronizers –globally asynchronous & locally synchronous use analog for digital –3D microwave techniques –“nano modems” ( more than just 1 and 0)

High-voltage digital I/O “high voltage” by design: 5.5V I/O in 2.5V technology ! [Annema, JSSSC,March 2001]

substrate bounce substrate L bondwire ground V dd

substrate bounce substrate L bondwire ground V dd

substrate bounce substrate L bondwire ground V dd

substrate bounce Even 100% digital chip has problems Decouple supply in digital ( 30% area!) –locally! Use package with low inductance Make very robust analog designs

Conclusion

conclusions Technology scaling > 10 years Scaling of analog and digital circuits fundamentally different problems can be solved by design Digital for analog and analog for digital