SKIROC New generation readout chip for ECAL M. Bouchel, J. Fleury, C. de La Taille, G. Martin-Chassard, L. Raux, IN2P3/LAL Orsay J. Lecoq, G. Bohner S. Manen, L. Royer IN2P3/LPC Clermont DESY CALICE meeting

13 fevrier 2007GMC -CALICE Meeting 2 SKIROC -> Silicon Kalorimeter Integrated Read Out Chip - ECAL read out - Silicon PIN detector - 36 channels - Compatible new DAQ 4.4mm 4.8mm

13 fevrier 2007GMC -CALICE Meeting 3 Main features Designed for 5*5 mm² pads 36 channels (instead of 72 to reduce cost of prototype) Detector AC/DC coupled Auto-trigger 2 gains / 12 bit ADC  2000 MIP Power pulsing  Programmable stage by stage Calibration injection capacitance Embedded bandgap for reference voltage Embedded DAC for trigger threshold Compatible with physic proto DAQ Serial analogue output External “force trigger” Probe bus for debugging 24 bits Bunch Crossing ID SRAM with data formatting Output & control with daisy-chain Digital on FPGA for tests

13 fevrier 2007GMC -CALICE Meeting 4 Block scheme of EUDET ECAL FEE Ch. 0 Ch. 1 Analog channel Analog mem. 36-channel Wilkinson ADC Analog channel Analog mem. Ch. 35 Analog channel Analog mem. Bunch crossing 24 bit counter Time digital mem. Event builder Memory pointer Trigger control Main Memory SRAM Com module ECAL SLAB Inside the chip

13 fevrier 2007GMC -CALICE Meeting 5 One channel description 20M 1M 200ns G=10 G=1 200ns Analog Memory Depth = 5 Analog Memory Depth = 5 G=100G=5 12 bits ADC Gain selection 0->6pF 3-bit threshold adjustment 10-bit DAC Common to the 36Channels T 100ns DAC Q HOLD Preamp Ampli Slow Shaper Fast Shaper Trigger Charge measurement 3pF Calibration input input

13 fevrier 2007GMC -CALICE Meeting 6 Trigger Whole chip triggered when 1 channel triggers External trigger for pedestal measurement Trigger threshold adjustable channel by channel : 10 bits common for global coarse tuning 3 bits fine tuning channel by channel

13 fevrier 2007GMC -CALICE Meeting 7 Analog memory : SCA Depth : 5 Architecture : Voltage write/ voltage read 1 buffer per capacitor Capacitor : 2pF Difficulty : storage is very long In Write Read Out Principle of a « voltage-write, voltage-read » analog memory

13 fevrier 2007GMC -CALICE Meeting 8 Wilkinson ADC Channel 0 Channel 1 Channel 71 Ramp generator Register 0 Register 71 Gray counter

13 fevrier 2007GMC -CALICE Meeting 9  Main characteristics  Fully differential structure (MC to MD input stage)  1V input dynamic range  12 bits output Gray code  Counting frequency: 50MHz  82µs conversion time  Power supply: 3.5V (analog) and 2.5V (digital)  Power consumption < 3mW  One channel submitted in september 06 LPCC ADC ©G. Bohner (LPCC)

13 fevrier 2007GMC -CALICE Meeting 10 LPCC Ramp ADC: layout (1 channel) 1700 um LVDS receiver12 bits Gray counter 12 bits output register 100 um Analog part ©G. Bohner (LPCC)

13 fevrier 2007GMC -CALICE Meeting 11 LPCC ADC : Linearity error (simulation) Input (V) Error (lsb) ©G. Bohner (LPCC)

13 fevrier 2007GMC -CALICE Meeting 12 Vref shaper INL (ADC count) vs Vin MAROC2 : Wilkinson ADC linearity (Backup)

13 fevrier 2007GMC -CALICE Meeting 13 SKIROC : dedicated to measurement Not designed for test beam but pure prototype 250 probing point embedded two 36 channel ADCs (LPCC + LAL as a backup) DAC 10 bits for threshold + 3 bits for fine tuning channel by channel Bandgap for reference voltages Digital on FPGA : flexibility

13 fevrier 2007GMC -CALICE Meeting 14 Conclusions Second generation ASIC for ECAL read-out exists now SKIROC was submitted on nov 06 It will come back in march 07 Test board is now in preparation Digital bloc will be in FPGA to be tested together