Analog to Digital Convertor MTT48 V1.0 ADC - 1 ANALOG TO DIGITAL CONVERTOR (ADC)

Analog to Digital Convertor MTT48 V1.0 ADC - 3 Module Objective Configure ADC for polled or interrupt operation Configure the control registers

Analog to Digital Convertor MTT48 V1.0 ADC - 4 Analog to Digital Convertor Module 14 Channels with Multiplexed Input Linear Successive Approximation 8 bit resolution Single or Continuous Conversion Conversion Complete Flag or Conversion Complete Interrupt Selectable ADC Clock

Analog to Digital Convertor MTT48 V1.0 ADC - 5 ADC Signals I/O Signals : 13 I/O pins (port B and D) ADC Analog Power Pin (V DDA ) ADC Analog Ground Pin (V SSA ) ADC Voltage Reference Pin (V DDAREF ) Power supply for setting the reference voltage V REFH ADC Voltage Reference High Pin (V REFH ) One of two reference supplies and is generated from V DDAREF with a value V DDAREF /2 ADC Voltage Reference Low Pin (V LOW ) Lower Reference Supply for ADC ADC Voltage In (ADVIN) Input voltage signal from one of the fourteen channels

Analog to Digital Convertor MTT48 V1.0 ADC - 6 ADC Block Diagram INTERNAL DATA BUS Read DDRB/DDRD DDRBx/DDRDx RESET Write DDRB/DDRD PTBx/PTDx Write PTB/PTD PTB/Dx Read PTB/PTD (ADC Channel 1) Disable Channel Select ADCH[4:0] ADC Successive Approximation Register ADC Data Register ADC Voltage In (ADVIN) Clock Generator ADC Clock Interrupt Logic Conversion Complete AIEN COCO/ID MAS Bus Clock CGMXCLK ADIV[2:0] ADICLK

Analog to Digital Convertor MTT48 V1.0 ADC - 7 Successive Approximations Method

Analog to Digital Convertor MTT48 V1.0 ADC - 8 A/D Conversion Successive Approximation Method

Analog to Digital Convertor MTT48 V1.0 ADC - 9 ADC Registers Three registers control and monitor ADC operations: ADC status and control register (ADSCR) ADC data register (ADR) ADC clock register (ADCLK)

Analog to Digital Convertor MTT48 V1.0 ADC - 10 ADC Clock RESET: WRITE: READ: ADCLK ADC Clock Presacler Bits (ADIV2:ADIV0) –Selects divide ratio used by ADC to generate internal ADC clock ADC Input Clock Select (ADICLK) –Selects either bus clock or CGMXCLK as input clock source 1 = Internal bus clock 0 = External clock (CGMXCLK) Please Note: Internal ADC Clock must not exceed 1MHz ADC Clock Register (ADCLK) ADICLK ADIV0ADIV1 ADIV

Analog to Digital Convertor MTT48 V1.0 ADC - 11 ADC Status and Control RESET: WRITE: READ: COCO/AEINADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 ADSCR Conversion Complete / Interrupt DMA Select (COCO/IDMAS) –Set when conversion is complete –Selects either CPU or DMA to service ADC interrupt request. –Cleared whenever ADC Status and Control Register is written or whenever the ADC Data Register is read. 1 = Conversion completed(AEIN=0) / DMA Interrupt (AEIN=1) 0 = Conversion not completed(AEIN=0) / CPU Interrupt (AEIN=1) ADC Interrupt Enable(AEIN) –Interrupt at end of ADC conversion 1 = ADC Interrupt Enabled 0 = ADC Interrupt Disabled ADC Continuous Conversion (ADCO) 1 = Continuous ADC conversion 0 = One ADC conversion ADC Channel Select Bits (ADCH[4:0]) –Select one of fourteen channels –If all bits are set to one ADC subsystem is turned off ADC Status and Control Register (ADSCR) IDMAS

Analog to Digital Convertor MTT48 V1.0 ADC - 12 ADC Channel Select

Analog to Digital Convertor MTT48 V1.0 ADC - 13 ADC Result ADC Data Register (ADR) –Contains 8-bit conversion result –Updated each time ADC conversion completes RESET:XXXXXXXX WRITE: READ: ADR AD7AD6AD5AD4 AD3 AD2AD1 AD0

Analog to Digital Convertor MTT48 V1.0 ADC Low Power Modes - WAIT ADC module remains active ADC registers are not accessible –Except to DMA ADC module interrupt can wake MCU STOP ADC module is inactive Any pending conversion is aborted Conversions resume when MCU exits stop mode after an extenal interrupt Allow one conversion cycle to stabilize the analog circuitry