How to Accelerate the Analog Design Verification Flow Itai Yarom Senior Verification Expert Synopsys

Where do we have analog blocks? A common SoC chip uses many IP’s –Like: USB, HDMI, etc. Each IP uses one or more analog blocks A certain analog block can be used in different IP’s –Therefore, we can have the same analog block but with different configuration 2

How good is verification flow for analog blocks? We want to find bugs as early as possible –Can we use the vast knowledge we have from logic verification world? 3

Goals Provide robust analog verification flow Agenda Analog designs verification challenges Alternative verification flow Results & Summary 4

Example: 3GHz ADPLL Reference : IEEE ISSCC 2012 ADPLL Block diagram

Is this a bug? The process of analyzing the results is complex –Done at post simulation time Reduces the variations checked 6

Analog vs. Digital simulation

Proposed Solution: SystemVerilog Associative Arrays Capture the signal values into an associative array Perform the analysis as part of the testbench during the simulation Benefits: –Faster runtime (x100 speedup) –Can run test hundreds of characteristics vs. tens before 8

An Example: Jitter Using SystemVerilog associative array –Jitter analysis is possible during simulation

Analog Style Analysis in VCS Using SystemVerilog associative array enable to perform analysis on the analog data at the end of the simulation 10

Mixed signal ‘regression’ flow The automatic evaluation as part of the testbench enable to test more complex scenarios –A scenarios is a random combination of the parameters to be checked

Results of ADPLL Jitter The ‘regression’ flow enable to tests over 200 combinations of parameters –A much more robust testing –X100 runtime improvement –A significant better QA quality 12 ParameterFull spice Regression w/ Discovery-AMS Sim Time for 15us >100 h1 h Number of Tests runs Up to 5Over 200 Post Analysis time 10 min per test none Effort - Manual, Sim Time, IT resources QA Coverage Full spice New flow: Discovery-AMS + regression Quality improvement

Summary There are many analog block in typical SoC design The verification process of analog blocks can be improved We used SystemVerilog associative arrays to enalbe in-sim analysis –Significant runtime and quality improvement This flow is being adopted in the industry 13

How to Accelerate the Analog Design Verification Flow Itai Yarom, Senior Verification Expert, Synopsys Thanks to Gabi Glasser for his contribution to this work

Abstract In this article we propose a method for simplifying analysis and increasing coverage during mixed signal simulations. Many checks in a simulation test bench can be implemented by relating to the value of a signal within a narrow window of time. When the intention is to analyze analog signals, the measurements are done many times on long vectors (e.g. RMS). This type of analysis cannot be implemented within the digital test-bench and is done using post processing methods. The method proposed here is to take advantage of SystemVerilog capabilities, which enable defining a hash (associative) array with unlimited size. During the simulation, vectors are created for required signals, allowing them to be analyzed within the test-bench along or at the end of the simulation, without need to save these signals into a file. The simplification of the analog style analysis paves the road to massive mixed signal simulation (i.e. regression testing). 15