HCC Analog Monitor HCC Design Review April 24, 2014 Mitch Newcomer Nandor Dressnandt Aditya Narayan Amogh Halergi Dawei Zhang* * Original design work
Strips System Requirements – Hybrid Power Regulated ~10mA with 7 monitored voltages. Readout Clock. (40MHz) Command Decoder readout functionality. Data Output path operational. Operation – Upload Monitored Limits, Masks for Flag warnings/Interlock settings Monitors Voltages and temp sensors 0-1V, 1.6ms cycle time. 10 bit monitor data available through Command Decoder request. Outputs – Optional (mask controlled) Flag in Data Stream Command decoder readout to Normal Data stream extracted by ROD Selectable HCC output can be used to disable Regulators on the FEIC’s Analog Monitor HCC Design Review April 24, 20142
Seven Channel Analog Monitor Selections SP Shunt Control ?? Other Vmeas HV return current measurement. HCC Design Review April 24, 2014 Gain 3
State machine counter scaled 40MHz clock gives 800ns integrator steps (~1mV) Zero Volt Reference pad to measure HCC reference. Counter driven Integrating DAC mV provides a common ramp for all comparator voltage inputs. When monitored voltage ≥ reference ramp on 2 consecutive steps. 10 bit Counter value Latched High and Low limits downloaded to HCC registers. Flip flop based warning flag in status word downloaded with each data packet. HCC may perform limit based Clock or Regulator Interlock function if enabled. Functional Blocks in Words HCC Design Review April 24, 20144
Simplified Integrating DAC early version Integrator Reset Capacitor Switch Control. Stair Case Counter Ramp DAC out Integrator cap HCC Design Review April 24, V 1V Autonomous Operation 5
Persistence Circuit DQ CLK DQ Latch Counter CO Comparator Clock Signal Check Valid Data Flag Reset Require two consecutive Over Threshold Readings HCC Design Review April 24, 20146
Limit Logic Counter Upper Limit Lower Limit D(0:8) DQ CLK DQ Data Valid Flag (Reset at start of each Ramp) SR bit “Exceeds Hi Limit” SR bit “Below Low Limit” Minimal logic exploits the counter scheme If Lower Limit Matches Counter after “Valid Data” Set Warning Flag If Upper Limit Matches Counter before “Valid Data” Set Warning Flag HCC Design Review April 24, 20147
Measurement Accessories NTC temp sensor Diode Temp Sensor HV return Current Measurement HCC Design Review April 24, 20148
Temperature Measurement NTC Diode Based Temp Measurement. ~2mV / degree C Offset Calibration Required. Offsets do not appear to be affected by radiation. HCC Design Review April 24, 20149
10K NTC Temp Meas. Example HCC Monitor NTC Thermister 25C External 75K resistor. Bandgap driven Ref. dV/d t > ~ 6mV -30C to 5C HCC Design Review April 24, µA leakage ~35mV offset Need lower R NTC 10
D iode B ased “HCC resident ” Temp Sensor -1.7 mV / C -50C 50C Need to Measure Offset / Confirm Slope HCC Design Review April 24,
HCC Implementation of Internal Temp Sensor HCC Design Review April 24,
Simulation of Implemented Diode Temp Module TempVout mV/ 0 C mV oCoC HCC Design Review April 24,
Sensor Return Current Amplifier Inverting Amp Input assumes Current pulled from a negative voltage ource. HCC Design Review April 24, 2014 Current from Negatively Biased Sensor. Note that protection diodes are a free line of defense if the opamp dies. Easily can handle 5mA. Default Turn on All swiches Hi ‘F’ 14
OpAmp adapted for 0utput current >5mA PMOS Input followers HCC Design Review April 24,
Frequency Response 3db corner 300KHz Hz Output Magnitudec Output Phase HCC Design Review April 24,
Full 5mA Range 5mA Leakage 1Volt output HCC Design Review April 24,
Summary The Autonomous monitor provides and automated measurement system able to monitor: HCC voltages Vraw, Vregulator, Vbandgap, 0V hybrid, Internal and external temperature, current returned from the Sensor and an optional external input Programmed limit sensing can Provoke an Action error flag, turn off hybrid clocks or even the ABCn regulator (both require 2 different enable bits in the HCC). Each of the channels may be masked to eliminate Action. HCC Design Review April 24,