Dracula Verification PDRACULA LOGLVS DRC-ERC Command File LVS Command File LPE Command File Schematic layout CDL Out GDS II Database PDRACULA CDL Netlist LOGLVS DRC/ERC LVS LVSLOGIC.DAT LPE SPICE01.DAT

Run Dracula LPE (I) 1. LPE netlist 的 node name 要跟 schematic 相對應，故工作目錄中應該含有以下三個檔案： 　MyCellName.db，LPE command file ( lpe.com ) 與 Schematic Netlist( CDL out 後的結果) 2.執行 LOGLVS 將 netlist 轉換成 LVSLOGIC.DAT 　此步驟於 LVS 中示範過，方法相同。 3.執行PDRACULA來Compile LPE command file(步驟和 DRC/ERC command file相同) 　(請確定前述的LVSLOGIC.DAT檔案已經產生) [vlsi20]:~/Dracula3m/Lpe>PDRACULA ******************************************************************************* */N* DRACULA3 ( REV. 4.51.0398 / SUN-4 S5R4 /GENDATE: 19-MAR-98/14 ) *** ( Copyright 1995, Cadence ) *** */N* EXEC TIME =13:45:08 DATE =13-APR-99 HOSTNAME = vlsi20 :/g lpe.com n :/f ** NOTE : NO OUTPUT NEEDED SO SETTING SUMMARY-ONLY=YES FOR THIS RUN ONLY ** CREATING : COMMAND FILE : jxrun.com ** NOTE : THIS JOB HAS 60 STAGES END OF DRACULA COMPILATIONS * 0.136 Mbytes allocated to the current process. * 0.000 Mbytes is still in use. * THE END OF PROGRAM TIME = 13:46:27 DATE =13-APR-99 *

Run Dracula LPE (II) 3. 執行 在 compile 完 command file 後若無任何錯誤會產生一個 jxrun.com的可執行檔 [vlsi20]:~/Dracula3m/Lpe>jxrun.com > lep.log& Ã 4. 檢視 產生LPE file之前DRACULA會先做LPECHK(類似 LVS)，要LPECHK 正確無誤才會產生LPE file。 以下為所轉出的LPE file 之例子 * * CADENCE/LPE SPICE FILE : SPICE01 * DATE : 13-APR-99 ****** MOS XTOR PARAMETERS FROM : 7MOSPNET *.EQUI CKIN=5 CLOCK=6 GND=0 NET18=9 NET22=8 NET23=7 NET37=13 NET42=19 *+ NET6=3 NET7=4 NET8=14 VDD=2 *.GLOBAL 0 2 .SUBCKT SPICE01 5 6 9 8 7 13 19 3 4 14

Run Dracula LPE (III) * *----- TOTAL # OF MOS TRANSISTORS FOUND : 41 M1 0 4 3 0 NCH L=0.60U W=1.20U AD=1.86P PD=5.50U AS=1.86P PS=5.50U M2 4 20 21 0 NCH L=0.60U W=1.20U AD=1.86P PD=5.50U AS=0.45P PS=1.95U M3 0 5 21 0 NCH L=0.60U W=1.20U AD=1.86P PD=5.50U AS=0.45P PS=1.95U M4 0 8 7 0 NCH L=0.60U W=66.00U AD=59.95P PD=98.80U AS=52.80P PS=85.20U * *----- TOTAL # OF MOS TRANSISTORS FOUND : 41 *----- COMMENTED : 0*不可以有COMMENTED 值存在* * 有 COMMENT 表示 Layout 上的 MOS 與 Schematic 上的 MOS 沒有完全對應，應該找出錯誤，後再重做 LPE* ******* DIODE PARAMETERS FROM : 7DIOPNET ****** RESISTORS PARAMETERS FROM : 7RESXNET *----- TOTAL # OF RESISTORS FOUND : 0 COMMENTED : 0 CC4 6 0 9.47862E-14 *所抽出的雜散電容* CC5 7 0 1.27599E-13 CC6 8 0 6.19163E-14 CC7 9 0 2.30853E-14 CC8 10 0 7.05999E-15 . *----- TOTAL # OF CAPS FOUND : 18 *----- COMMENTED : 0 .ENDS

Post Layout Simulation (post-sim) Two Methods of Post Layout Simulation (post-sim) Layout Parameter Extraction (LPE) [Spice Netlist] EPIC power mill time mill path mill HSPICE

Post-Sim Using HSPICE Pre-Sim Spice file Post-Sim Spice file Title--Optimize Buffer Size with Wire Load 160fF .inc '/vlsi-proj/mtpv1/Spice/model0.6V2' *Netlist CC0 Z gnd! 3.9e-12 $[CP] MM5 net19 net27 vdd! vdd! PM W=76.8e-6 L=600e-9 M=1.0 MM4 Z net19 vdd! vdd! PM W=315e-6 L=600e-9 M=1.0 MM2 net31 I vdd! vdd! PM W=4.8e-6 L=600e-9 M=1.0 MM0 net27 net31 vdd! vdd! PM W=19.2e-6 L=600e-9 M=1.0 MM7 net19 net27 gnd! gnd! NM W=38.4e-6 L=600e-9 M=1.0 MM6 Z net19 gnd! gnd! NM W=146e-6 L=600e-9 M=1.0 MM3 net31 I gnd! gnd! NM W=2.4e-6 L=600e-9 M=1.0 MM1 net27 net31 gnd! gnd! NM W=9.6e-6 L=600e-9 M=1.0 *Parameters .param supply=3.3 freq=300MEG +t_ini=2.0n t_rf=0.5n t_cycle='1/freq' *+t_width='t_cycle-1.1n' +t_width='(t_cycle-2*t_rf)/2' *Independent/Dependent Power Supply vpower vdd! gnd! supply *Input Signal vin I 0 pulse(0 supply t_ini t_rf t_rf t_width t_cycle) . Title--Optimize Buffer Size with Wire Load 160fF .inc '/vlsi-proj/mtpv1/Spice/model0.6V2' *Netlist CC0 Z gnd! 3.9e-12 $[CP] M21 0 I 9 0 NM L=0.60U W=4.80U AD=6.72P PD=12.40U AS=6.72P PS=12.40U M75 vdd I 9 vdd PM L=0.60U W=12.20U AD=17.08P PD=27.20U AS=17.08P PS=27.20U M17 0 9 8 0 NM L=0.60U W=19.60U AD=22.05P PD=38.40U AS=15.68P PS=26.00U M71 vdd 9 8 vdd PM L=0.60U W=48.00U AD=54.00P PD=81.00U AS=38.40P PS=54.40U M4 0 8 7 0 NM L=0.60U W=66.00U AD=59.95P PD=98.80U AS=52.80P PS=85.20U M58 vdd 8 7 vdd PM L=0.60U W=159.60U AD=144.97P PD=208.00U AS=128.48P PS=185.20U M16 0 7 6 0 NM L=0.60U W=136.00U AD=124.95P PD=184.70U AS=108.80P PS=148.80U M47 vdd 7 6 vdd PM L=0.60U W=480.00U AD=420.00P PD=614.00U AS=384.00P PS=492.80U *Parameters .param supply=3.3 freq=300MEG +t_ini=2.0n t_rf=0.5n t_cycle='1/freq' *+t_width='t_cycle-1.1n' +t_width='(t_cycle-2*t_rf)/2' *Independent/Dependent Power Supply vpower vdd! gnd! supply