EEL-6167 VLSI DESIGN SPRING 2004 TERM PROJECT Mirror Circuits: Design and Simulation Craig Chin Miguel Alonso Jr.

Overview  The theory behind mirror-circuit logic design is introduced.  The method and tools involved in the simulation and layout of the various logic circuits are discussed.  The simulation circuits, the circuit layouts, and the simulation results are presented.  Observations pertaining to the design process and the simulation results are discussed.

Introduction  Mirror circuits are based on series-parallel configurations of MOSFETs.  A mirror circuit has the same transistor topology for the nFETs and the pFETs (refer to Figure 1).  NAND2, NOR2, EXOR2, or EXNOR2 logic gates can be constructed using the same mirror circuit structure.  The different functionalities are implemented by varying the inputs at each gate.  Only one general layout is necessary.  This simplifies the layout process.

Introduction Figure 1- Mirror Circuit for (a) Inverter and (b) Generic two input logic gate

Introduction  The rise times and fall times of the EXOR and EXNOR mirror circuit gates are shorter than their AOI counterparts.  However, the rise times and fall times the mirror circuit AND and NOR gates are slightly longer (see Table 1).

Introduction Table 1- Rise Times and Fall times of Mirror Circuits vs. Conventional Circuits

Method  The circuits to be explored were designed using Orcad’s PSPICE for the circuit simulation, and the LASI utility for designing the physical layout.  provides information on design rules for various processes, along with the scalable CMOS (SCMOS) design rule set.  A scalable CMOS (SCMOS) design rule set is based on reference measurement lambda (λ), which has units in microns.  All of the dimensions in the layout are written in the form Value = mλ  The layer maps used are shown in Figures 2 and 3.

Method Figure 2- Layer Map for SCMOS

Method Figure 3- Layer Map for SCMOS (cont'd)

Method  LASI is available free from  This tool combines the layout process with PSPICE, giving a very accurate representation of the physical model using SPICE.  It auto-routes layouts, calculates parasitic capacitances, and provides circuit files for use during SPICE simulation.  It has the capability of performing design rule checks for a set of design rules.  ORCAD simulations provides the advantage of the hierarchical circuit structures, where design takes place using sub-circuits.  The Taiwan Semiconductor Manufacturing Corporation (TSMC) was chosen to be the process, because their process parameters were the only ones available on the Mosis website.

Method  With the process parameters already defined, in order to provide an accurate model for simulation, the length and width of the NFET and PFET were specified to be: L n = 0.7um, W n = 1.4um, L p = 0.7um, W p = 3.5um  The (W/L) ratio for the NFET is 2 and for the PFET is 5, in order to maintain the device trans-conductance’s the same.  These values, in addition to the SPICE model parameters, are used for performing the circuit simulations for the Inverter, NAND, NOR, EXOR, and the D Flip Flop.

Circuit Diagrams and Layouts Figure 4-NMOS FET Layout Figure 5- PMOS FET Layout

Circuit Diagrams and Layouts Figure 4 – Inverter Circuit Diagram Figure 5 – Inverter Layout

Circuit Diagrams and Layouts Figure 6 – NAND2 Circuit Diagram Figure 7 – NAND2 Layout

Circuit Diagrams and Layouts Figure 8 – Edge-Triggered D Flip-Flop Circuit Diagram

Circuit Diagrams and Layouts Figure 9 – D Latch Sub-circuit Diagram Figure 10 – Inverter Sub-circuit Diagram

Circuit Diagrams and Layouts Figure 11 – Edge-Triggered D Flip-Flop Layout

Results of Simulation Figure 13 – Inverter Simulation at 10MHz Figure 12 – Inverter Simulation at 1MHz

Results of Simulation Figure 14 – Inverter Simulation at 100MHz

Results of Simulation Figure 16 – NAND2 Simulation at 10MHz Figure 15 – NAND2 Simulation at 1MHz

Results of Simulation Figure 17 – NAND2 Simulation at 100MHz

Results of Simulation Figure 19 – Edge-Triggered D Flip-Flop Simulation at 10MHz Clock Figure 18 – Edge-Triggered D Flip-Flop Simulation at 1MHz Clock

Results of Simulation Figure 20 – Edge-Triggered D Flip-Flop Simulation at 100MHz Clock

Results of Simulation  At 100 MHz The rise time for the inverter was.24 ns The fall time for the inverter was 0.04 ns The propagation delay for the D Flip Flop was 2.72 ns The rise time for the D Flip Flop was 2.02 ns The fall time for the D Flip Flop was ns

Discussion  Mirror Circuits were investigated using the various tools  The advantage of using mirror circuits comes in the layout process  Mirror circuits do, however, experience changes in the rise and fall times when compared to their minimal realization counter parts  This is evident from the simulation plots

Conclusion  In general, in order to improve the performance of the various circuits Select a better process that allows for smaller geometries Since the SCMOS design convention was used, there is no need to redesign the layouts, it is simply a matter of rescaling them Perhaps, if the above does not improve performance, the placement of the various sub-cells can be improved to minimize metalization paths