1 Final Year Project Development of method for improving the light-load efficiency of VRM’s Project Supervisor : Dr. Maeve Duffy March 2009.

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Presentation transcript:

1 Final Year Project Development of method for improving the light-load efficiency of VRM’s Project Supervisor : Dr. Maeve Duffy March 2009

2 VRM Voltage Regulator Module Voltage Regulator Module Switching Mode Power Supply for Microprocessor Switching Mode Power Supply for Microprocessor The most suitable topography for a VRM is a Multiphase Synchronous Buck Converter The most suitable topography for a VRM is a Multiphase Synchronous Buck Converter

3 Microprocessor Light Load Power States Optimize the runtime power consumption Power States Optimize the runtime power consumption Sleep States Idle Power Managements Sleep States Idle Power Managements

4 Trends in VRM Design is Microprocessor Loads Moore’s Law will apply into the future - Intel Moore’s Law will apply into the future - Intel Lower core voltages and higher currents Lower core voltages and higher currents Analysis of recent VRM guideline from Intel Analysis of recent VRM guideline from Intel Design Guideline VRM 9.1 VRM 10.0 VRM 11.0 Release Date Icc75A85A130A Icc(max)81A100A150A Icc(step)54A70A100A dIcc/dt450A/uS560A/uS1200A/uS VID V V V

5 Synchronous Buck Converter Efficiency Sources of Losses in the power stage Upper and Lower MOSFET s Upper and Lower MOSFET s Output Inductor Output Inductor Output Capacitor Output Capacitor

6 Analysis of MOSFET Losses Conduction for Losses for Upper and Lower MOSFET s Conduction for Losses for Upper and Lower MOSFET s Switching Losses for Upper MOSFET Switching Losses for Upper MOSFET Lower MOSFET Body Diode conduction losses Lower MOSFET Body Diode conduction losses Reverse Recovery Losses Reverse Recovery Losses Gate Driver Losses Gate Driver Losses

7 Capacitor and Inductor Losses Inductor Losses DCR and ACR DCR and ACR Hysteresis Losses Hysteresis Losses Eddy Current Losses Eddy Current Losses Capacitor Losses ESR (Equivalent Series Resistance) ESR (Equivalent Series Resistance)

8 SPICE Modelling of Power Losses Objective is to use SPICE to measure MOSFET switching losses from the instantaneous products of current and voltage

9 Shoot Through during Upper MOSFET Switch On Drain Source Current Upper ON Upper OFF Upper ON Upper OFF

10 Eliminating Shoot Through Introduction of dead eliminated shoot though on lower MOSFET switch on but not on upper MOSFET switch on Introduction of dead eliminated shoot though on lower MOSFET switch on but not on upper MOSFET switch on A possible cause of shoot through on upper MOSFET switch on is Dv/dt induced turn on of lower MOSFET. A possible cause of shoot through on upper MOSFET switch on is Dv/dt induced turn on of lower MOSFET. Alan Elbanhawy - Fairchild Semiconductor Alan Elbanhawy - Fairchild Semiconductor

11 Dv/dt Induced Turn On of Lower MOSFET

12 MathCAD Efficiency Calculator MathCAD displays equation and expression in graphically form, and is aware of SI units. Easier to track calculations in MathCAD MathCAD displays equation and expression in graphically form, and is aware of SI units. Easier to track calculations in MathCAD Used a MathCAD worksheet to calculate the efficiency of a single phase of a synchronous buck converter Used a MathCAD worksheet to calculate the efficiency of a single phase of a synchronous buck converter The original MathCAD worksheet was a supplement to a paper called “What MOSFET Can Do to Boost the Performance of VRM Design” The original MathCAD worksheet was a supplement to a paper called “What MOSFET Can Do to Boost the Performance of VRM Design” Alan Miftakhusdinov - Texas Instruments Alan Miftakhusdinov - Texas Instruments

13 Generating Rds(0n) from SPICE MOSFET Model Rds (0N) for upper and lower MOSFET s

14 Distributed Inductors Paralleling the output inductor Paralleling the output inductor Investigating if losses are reduced if inductor are switched out during periods of light loads Investigating if losses are reduced if inductor are switched out during periods of light loads The effective inductance of the output inductor changes when inductors are switched out. The effective inductance of the output inductor changes when inductors are switched out.

15 Effects of changing inductance of Output Ripple Current Output Ripple Current Output Capacitor ESR Losses Output Capacitor ESR Losses ILIL Increasing L Reducing L IoIo

16 Conclusion Using Distributed Inductor and switching out inductor during periods of light load does improve VRM efficiency

17 Questions