ECE 3130 – Digital Electronics and Design Lab 4 VTC and Power Consumption Fall 2012 Allan Guan.

Slides:



Advertisements
Similar presentations
ECE 3130 – Digital Electronics and Design
Advertisements

Digital to Analog Converter By Rushabh Mehta Manthan Sheth.
Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter CMOS INVERTER.
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Lecture 28 Field-Effect Transistors.
Courtesy : Prof Andrew Mason CMOS Inverter: DC Analysis By Dr.S.Rajaram, Thiagarajar College of Engineering.
Using Spice in Lab Practicing for Analog ASIC Design Goran Jovanović, Faculty of Electronic Engineering University of Niš Serbia and Montenegro.
The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering ECE122 Lab 4: VTC & Power.
PSPICE - Review Kishore C. Acharya. Kishore Acharya2 Starting Simulation with PSPICE Launch PSPICE design Manager Create a New Work Space or Open an Existing.
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response
11/5/2004EE 42 fall 2004 lecture 281 Lecture #28 PMOS LAST TIME: NMOS Electrical Model – NMOS physical structure: W and L and d ox, TODAY: PMOS –Physical.
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response Credits: David Harris Harvey Mudd College (Material taken/adapted from Harris’ lecture.
Lecture #24 Gates to circuits
Design and Implementation of VLSI Systems (EN0160) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley.
1 Lab Equipment. 2 TopicSlides DC Power Supply3-4 Digital Multimeter5-8 Function Generator9-12 Scope – basic controls13-20 Scope – cursors21-24 Scope.
Switching-Mode Regulators
S. Reda VLSI Design Design and Implementation of VLSI Systems (EN1600) lecture09 Prof. Sherief Reda Division of Engineering, Brown University Spring 2008.
CMOS VLSI Design4: DC and Transient ResponseSlide 1 EE466: VLSI Design Lecture 05: DC and transient response – CMOS Inverters.
EE4800 CMOS Digital IC Design & Analysis
EE 447 VLSI Design 4: DC and Transient Response1 VLSI Design DC & Transient Response.
Field-Effect Transistors 1.Understand MOSFET operation. 2. Understand the basic operation of CMOS logic gates. 3. Make use of p-fet and n-fet for logic.
The CMOS Inverter Slides adapted from:
Digital Integrated Circuits© Prentice Hall 1995 Inverter THE INVERTERS.
ECE 3130 – Digital Electronics and Design Lab 3 Multiplexers, Parity Generators, and Boolean functions using MUX Fall 2012 Allan Guan.
MOS Inverter: Static Characteristics
A.1 Large Signal Operation-Transfer Charact.
Mary Jane Irwin ( ) Modified by Dr. George Engel (SIUE)
Electronic Circuits Laboratory EE462G Lab #7 NMOS and CMOS Logic Circuits.
ECE 3130 – Digital Electronics and Design
Lecture bases on CADENCE Design Tools Tutorial
1. Department of Electronics Engineering Sahand University of Technology NMOS inverter with an n-channel enhancement-mode mosfet with the gate connected.
The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering ECE122 – 30 Lab 5: Layout.
THE INVERTERS. DIGITAL GATES Fundamental Parameters l Functionality l Reliability, Robustness l Area l Performance »Speed (delay) »Power Consumption »Energy.
The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering ECE122 Lab 4: VTC & Power.
Chapter 07 Electronic Analysis of CMOS Logic Gates
ECE122 – Digital Electronics & Design
Tanner Tools Tutorial S-Edit v13.0 Tutorial.
The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering ECE122 – 30 Lab 3: Layout.
ECE4430 Project Presentation
ELECTRICA L ENGINEERING Principles and Applications SECOND EDITION ALLAN R. HAMBLEY ©2002 Prentice-Hall, Inc. Chapter 12 Field-Effect Transistors Chapter.
Module 2 : Behavioral modeling TOPIC : Modeling a Digital pulse UNIT 1: Modeling and Simulation.
Electronic Circuits Laboratory EE462G Lab #5 Biasing MOSFET devices.
Introduction to CMOS VLSI Design MOS devices: static and dynamic behavior.
Objectives Understand the design environment and flow
© Digital Integrated Circuits 2nd Inverter EE5900 Advanced Algorithms for Robust VLSI CAD The Inverter Dr. Shiyan Hu Office: EERC 731 Adapted.
1 Parametric analysis Overview This course describes how to set up parametric and temperature analyses. Parametric and temperature are both simple multi-run.
Digital Integrated Circuits A Design Perspective
Introduction to PSpice
Introduction to MicroElectronics
Electronic Circuits Laboratory EE462G Lab #7 NMOS and CMOS Logic Circuits.
1. Digital cmos.2 10/15 Figure 10.1 Digital IC technologies and logic-circuit families. Digital IC Technologies CMOS & Pass Transistor Logic dominate.
MOSFET DC circuit analysis Common-Source Circuit
Solid-State Devices & Circuits
L 05 29Jan021 EE Semiconductor Electronics Design Project Spring Lecture 05 Professor Ronald L. Carter
EE210 Digital Electronics Class Lecture 8 June 2, 2008.
Tera-Pixel APS for CALICE Progress meeting, 6 th June 2006 Jamie Crooks, Microelectronics/RAL.
The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering ECE122 – 30 Lab 2: NAND gate.
ECE122 – Digital Electronics & Design Tanner Tools Tutorial Ritu Bajpai September 4, 2008.
CMOS 2-Stage OP AMP 설계 DARK HORSE 이 용 원 홍 길 선
It’s always important that all of your nodes be numbered. So the way to do that is to go to Options at the top of the screen then select Preferences. When.
Switching-Mode Regulators
ECE 3130 Digital Electronics and Design
THE CMOS INVERTER.
VLSI System Design DC & Transient Response
Electronic Circuits Laboratory EE462G Lab #6
Week 9: Series RC Circuit
Week 9a OUTLINE MOSFET ID vs. VGS characteristic
Introduction to CMOS VLSI Design Lecture 5: DC & Transient Response
Week 9a OUTLINE MOSFET ID vs. VGS characteristic
Lecture #17 (cont’d from #16)
Presentation transcript:

ECE 3130 – Digital Electronics and Design Lab 4 VTC and Power Consumption Fall 2012 Allan Guan

Today’s Lab Plot VTC for an inverter Check if VTC is symmetric If VTC is not symmetric we will find Wp/Wn such that the VTC for an inverter is symmetric Allan Guan

What is VTC? Voltage Transfer Curve Plots output voltage vs. input voltage Symmetry – when a line plotted through the origin and Vdd/2 intersects the VTC at Vdd/2 Allan Guan

Plotting the VTC Open your inverter test bench from the 1 st lab Replace the pulse input with a DC source Use the net label to label “in” and “out” of the inverter Allan Guan

Simulation Settings Select DC sweep analysis Set the source name to the name of your inverter’s input source (IMPORTANT: add a ‘v’ in front of the name!) Click OK, do NOT simulate Allan Guan

T-Spice Click the “Open in T-Spice” button (T-icon to the right of the green play button) Add the following lines of code Hit the green play button That vertical line is just the cursor, ignore that Allan Guan

The VTC is not symmetric  Allan Guan

Obtaining a Symmetric VTC Keeping the length and width of the NMOS fixed we can vary the width of the PMOS to obtain a symmetric curve To do so, we will perform a DC sweep like before but with the addition of the parametric sweep Allan Guan

Setting up the Parametric Sweep Allan Guan

Defining the pMOS width as a parameter In the T-Spice code, write.param width=3u In the pMOS properties, change W=3u to W=‘width’ Now, the pMOS width is defined by parameter ‘width’ Allan Guan

Your T-Spice code should look like this Allan Guan

Parametric Sweep Waveform Allan Guan

Designing with Symmetric VTC Click the trace to determine the width required for the symmetric VTC Record the width of the pMOS corresponding to the symmetric operating point (you should get 3.2u) Replace the inverter input with the original Pulse source Go back to simulation settings and uncheck the DC and parameter sweep and select Transient Analysis Open up the T-Spice command window and substitute this width for the pMOS and simulate Allan Guan

Rise/Fall Symmetric Operation In the W-Edit window, go to the waveform calculator Click “Measures…” and select “rise time” Type in a trace name and press “Measure” With the same trace, measure the “fall time” Since we changed the pMOS width to obtain a symmetric VTC, the rise and fall times should be the same Allan Guan

Power Consumption Now, we will use Tanner Tools to estimate the power consumption of a design We will also identify the sources of that consumption Allan Guan

Power Consumption Simulate the circuit over 2 periods with fine resolution (2ns) Show the waveforms for: – The input and output voltages – The power provided by the power supply – The currents drawn from the power supply and the capacitor Allan Guan

Plotting Power and Current from the Transient Analysis Allan Guan Get this capacitor from the Devices library

Power 10 pF load and 10ns rise time Allan Guan

Power 1 pF load and 10ns rise time Allan Guan

Power 1 pF load and 1ns rise time Allan Guan

Analysis Report numerical values of your results in tabular form. Can we vary the width of NMOS instead of PMOS in order to obtain symmetric VTC? If yes, should we increase or decrease it’s value keeping PMOS width fixed? On the VTC of the inverter, show the triode, saturation, and cut-off region. Which region is used for digital design and which one is used for analog design? Allan Guan

Analysis (Continued) Do you obtain different values of power consumed on varying the load and rise/fall time of the pulse? Compare and analyze your results. Allan Guan