Lecture 4 CMOS Inverter

References Section 4.2,4.3,4.6 (Hodges)

5 Regions of Operations I: N(off), P(lin) As you increase Vin from 0 V to 1.8 V, you progress from region I to region V.

Current Draw of a CMOS Inverter

Ideal Voltage Transfer Characteristics of an Inverter Large Input Range/Small Output Range →Noise Immunity. Range: the voltage interval over which the signal is either a 1 or a 0.

Practical VTC of an Inverter Gain=ΔV out /ΔV in Not GND V S is defined by V out =V in

Effect of Input Noise on the Output

Noise Margin Output of the Driving Stage Input of the Receiving Stage

Unity Gain Noise Margin Definitions NM L =V IL -V OL NM H =V OH -V IH If V in >V IL, the gain exceeds unity and the output begins to drop significantly.

General Analysis Methodology Region I: N-OFF, P-Triode Region II: IDN(Sat)=IDP(Triode)→V IL (Cumbersome to calculate analytically) Region III: IDN(Sat)=IDP(Sat)→V S (Switching voltage) Region IV: IDN(Triode)=IDP(Sat) →V IH (Cumbersome to calculate analytically) Region V: N-Triode, P-OFF

Current Consumed by a CMOS Inverter

TSMC 0.18 um Example W N /L N =200nm/200nm W P /L P =200nm/200nm

Computation of V S See Derivation in the Handout Assume: – 0.18 um TSMC CMOS – W N /L N =200nm/200nm; W P /L P =200nm/200nm – E CN L N =4.8V; E CP L P =1.2V Hand Analysis using (EQ 4.15 /EQ 4.14): 0.76V Spice: V

VS of TSMC 0.18 um Assume: 0.18 um TSMC CMOS W N /L N =200nm/200nm W P /L P =200nm/200nm

Adjust V S Knob: – χ as defined in EQ – Increase W N L P /L N W P → Decreased V S. – Decrease W N L P /L N W P → Increased V S.

Increase W P to adjust V S W N /L N =200nm/200nm W P /L P =200nm/200nm W N /L N =200nm/200nm W P /L P =460nm/200nm

Noise Margin V OH =VDD V OL =0 V Determine V IL and V IH from the -1 slope.

V IL W N /L N =200nm/200nm W P /L P =460nm/200nm

V IH W N /L N =200nm/200nm W P /L P =460nm/200nm

NM Calculation Process: TSMC 0.18 um – W N /L N =200nm/200nm; W P /L P =460nm/200nm V S =0.809 V V OH =1.8 V V OL =0 V V IL =0.66 V V IH =0.905V NM L =V IL -V OL =0.66 V-0V=0.66V NM H =V OH -V IH =1.8 V-0.905V=0.895 V

50% Propagation Delay

Propagation Delay of CMOS Inverter 50% Propgation Dealay: 0.69 R eff C L

CMOS Inverter Calculation

t PHL Δt=C L ΔV/(I DS ) – ΔV=V DD /2 (from V DD to V DD /2) – I DS NMOS is in Saturation (Hand Out) t pHL =0.69R effn C L t pHL =C L ΔV/(I DSAT ) R effn =(V DD /2)/(0.69I DSAT )

t PLH Δt=C L ΔV/(I DS ) – ΔV=V DD /2 (from 0 to V DD /2) – I DS PMOS is in Saturation (Hand Out) t pLH =0.69R effp C L t pLH =C L ΔV/(I DSAT ) R effp =(V DD /2)/(0.69I DSAT )

R eff Comparison for 0.18 um Process 0.18 um NMOS0.18 um PMOS Reff,calc (kOhm/SQ) Reff,list (kOhm/SQ) Reff: unit is Kohm/SQ R N =R effN (L N /W N ) R P =R effP (L P /W P )

Design Example Design Constraints: – t PHL <50 pS, t PLH <50 pS – Load Capacitor: 50 fF – Use minimum W and L to attain the specs. Determine W/L for PMOS and NMOS Method: – t PHL =t PLH =50 pS=0.7R eff C L – Use R effn =12.5 KOhm/SQ and R effp =30 KOhm/SQ – Reff=1.4 Kohm – Reff=R effn (L n /W n ); Reff=R effp (L p /W p ) – Use minimum L n. – W n =1.784 um; W p =4.284 um

tPLH

t PHL