VLSI Design Lecture 2: Basic Fabrication Steps and Layout Mohammad Arjomand CE Department Sharif Univ. of Tech. Adapted with modifications from Harris’s lecture notes

Outline How to make a transistor or a gate Layout Design rules Cross-section Top view (masks) Fabrication process Layout Design rules Standard cell layouts Stick Diagrams

Our technology We will study a generic 180 nm technology (SCMOS rules). Assume 1.2V supply voltage. Parameters are typical values. Parameter sets/Spice models are often available for 180 nm, harder to find for 90 nm. SCMOS is unusual in that it is not a single fabrication process, but a collection of rules that hold for a family of processes. Using generic technology rules gives greater flexibility in choosing a manufacturer for your chips. It also means that the SCMOS technology is less aggressive than any particular fabrication process developed for some special purpose—some manufacturers may emphasize transistor switching speed, for example, while others emphasize the number of layers available for wiring.

Fabrication services Educational services: U.S.: MOSIS (has defined SCMOS rules) EC: EuroPractice Taiwan: CIC Japan: VDEC Foundry = fabrication line for hire. Foundries are major source of fab capacity today. MOSIS: MOS Implementation Service. MOSIS is now an independent commercial service.

Silicon Lattice Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors

Dopants Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V (Arsenic, Phosphorus): extra electron (n-type) Group III (Boron): missing electron, called hole (p-type)

p-n Junctions A junction between p-type and n-type semiconductor forms a diode. Current flows only in one direction N-Diff P-Diff anode cathode

Fabrication processes IC built on silicon substrate: some structures diffused into substrate; other structures built on top of substrate. Substrate regions are doped with n-type and p-type impurities. (n+ = heavily doped) Wires made of polycrystalline silicon (poly), multiple layers of aluminum (metal). Silicon dioxide (SiO2) is insulator. Aluminum, tungsten, and other metals are used for metal close to the silicon. Copper is a better conductor but it is a poison to semiconductors, so it is used only in higher layers. Chips with copper interconnect include a special protection layer between the substrate and the first layer of copper. That layer prevents the copper from entering the substrate during processing. Glass insulation lets the wires be fabricated on top of the substrate using processes like those used to form transistors. The integration of wires with components, which eliminates the need to mechanically wire together components on the substrate, was one of the key inventions that made the integrated circuit feasible.

CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or etched Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process

CMOS Inverter

Inverter Cross-section Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors

Well and Substrate Taps Substrate must be tied to GND and n-well to VDD Metal to lightly-doped semiconductor forms poor connection called Shottky Diode Use heavily doped well and substrate contacts / taps

Inverter Mask Set Transistors and wires are defined by masks Cross-section taken along dashed line

Detailed Mask Views Six masks n-well Polysilicon n+ diffusion p+ diffusion Contact Metal

Fabrication Steps Start with blank wafer Build inverter from the bottom up First step will be to form the n-well Cover wafer with protective layer of SiO2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO2

Oxidation Grow SiO2 on top of Si wafer 900 – 1200 C with H2O or O2 in oxidation furnace

Photoresist Spin on photoresist Photoresist is a light-sensitive organic polymer Softens where exposed to light

Lithography Expose photoresist through n-well mask Strip off exposed photoresist

Etch Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed

Strip Photoresist Strip off remaining photoresist Use mixture of acids called piranah etch Necessary so resist doesn’t melt in next step

n-well n-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si Ion Implanatation Blast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Si

Strip Oxide Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps

Polysilicon Deposit very thin layer of gate oxide < 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH4) Forms many small crystals called polysilicon Heavily doped to be good conductor

Polysilicon Patterning Use same lithography process to pattern polysilicon

Self-Aligned Process Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and n-well contact

N-diffusion Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing

N-diffusion cont. Historically dopants were diffused Usually ion implantation today But regions are still called diffusion

N-diffusion cont. Strip off oxide to complete patterning step

P-Diffusion Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact

Contacts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed

Metalization Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires

Simple cross section SiO2 metal3 metal2 metal1 transistor via poly n+ substrate n+ p+ metal1 poly SiO2 metal2 metal3 transistor via

Photolithography Mask patterns are put on wafer using photo-sensitive material: Features are patterned on the wafer by a photolithographic process; the wafer is covered with light-sensitive material called photoresist, which is then exposed to light with the proper pattern. The patterns left by the photoresist after development can be used to control where SiO2 is grown or materials are placed on the surface of the wafer. Photolithographic processing steps are performed using masks which are created from the layout information supplied by the designer. In simple processes there is roughly one mask per layer in a layout, though in more complex processes some masks may be built from several layers while one layer in the layout may contribute to several masks.

Process steps First place tubs (wells) to provide properly-doped substrate for n-type, p-type transistors. a twin-tub process: p-tub n-tub substrate The wells prevent undesired conduction from the drain to the substrate. (Remember that the transistor type refers to the minority carrier which forms the inversion layer, so an n-type transistor pulls electrons out of a p-tub.) Regions on the wafer are selectively doped by implanting ionized dopant atoms into the material, then heating the wafer to heal damage caused by ion implantation and further move the dopants by diffusion.

Process steps, cont’d. Pattern polysilicon before diffusion regions: gate oxide poly poly p-tub n-tub The next steps form an oxide covering of the wafer and the polysilicon wires. The oxide is formed in two steps: first, a thick field oxide is grown over the entire wafer. The field oxide is etched away in areas directly over transistors; a separate step grows a much thinner oxide which will form the insulator of the transistor gates. After the field and thin oxides have been grown, the polysilicon wires are formed by depositing polysilicon crystalline directly on the oxide. Originally, Al gate was used for the MOSFETs, but soon poly Si gate replaced it because of the adaptability to the high temperature process and to the acid solution cleaning process of MOSFET fabrication. Especially, poly gate formation step can be put before the S=D (source and drain) formation. This enables the easy self-alignment of S=D to the gate electrode.

Process steps, cont’d Add diffusions, performing self-masking: poly p-tub n+ n+ n-tub p+ p+ Diffusion wires are laid down immediately after polysilicon deposition to create self-aligned transistors—the polysilicon masks the formation of diffusion wires in the transistor channel. For the transistor to work properly, there must be no gap between the ends of the source and drain diffusion regions and the start of the transistor gate. If the diffusion were laid down first with a hole left for the polysilicon to cover, it would be very difficult to hit the gap with a polysilicon wire unless the transistor were made very large.

Process steps, cont’d Start adding metal layers: metal 1 metal 1 vias poly poly p-tub The tub structure means that n-type and p-type wires cannot directly connect. Since the two diffusion wire types must exist in different type tubs, there is no way to build a via which can directly connect them. Connections must be made by a separate wire, usually metal, which runs over the tubs. After the diffusions are complete, another layer of oxide is deposited to insulate the polysilicon and metal wires. n+ n+ n-tub p+ p+