CINCINNATI, FNAL, HAWAII, LBNL, PRINCETON, SLAC, VPI KEK, NAGOYA, NIIGATA, OSAKA,SAGA, TOHOKU, TOKYO, TMU, TSUKUBA Detector R&D

Contributions by US and JPN (recent 6 years) Cherenkov PID & advanced photon sensors  High speed MCP PMT (SLAC, Nagoya)  Focusing DIRC prototype (SLAC, Cincinati)  GaAs photocathode, TOP (Nagaoya)  144 ch HPD for RICH counter(Nagoya) MPGD related technology  GEM and MicroMEGAS for TPC read out (Saga,LBNL,KEK)  Gas PMT with microMEGAS structure (TMU,SLAC) Silicon detector technologies for thin trackers  Development of light weight silicon strip ladder, high heat conducting readout hybrid(Princeton)  Continuous Acquisition Pixel (CAP) sensor(Hawaii)  EMI from short bunch beam (Tohoku/KEK/SLAC)  Development of fine pitch flexible circuit (Niigata)  Striplet sensor (KEK)  Ladder assembly(KEK)  SOI pixel

Photon Sensors for Partilce ID MCP PMT for ultimate timing resolution Focusing DIRC counter with MCP-PMT Multi-pixel HPD for RICH in magnetic field GasPMT

Best timing sensors for single photon sensitivity even in a high B (SLAC,TMU)  MCP-PMT (Burle85011) It is possible to reach a resolution of  ~ 50ps at 15kG.

The first demonstration of the Focusing DIRC prototype (SLAC)

AC RICH with 144ch HPD (Nagoya) This corresponds to 144 ch HAPD arrangement in inner layer of real ARICH (almost) Minimum distance between HAPDs ~1.0mm ~13.1mrad 6 Pixel APD MultiAlkali photocathode Photon

Gas PMT (TMU) Stable operation of a bi- alkali photocathode was established.  Long term test (one year): No change in QE. Performance of a double Micromegas PMT in a high magnetic field.  Even in 90 deg. (parallel to the window surface) 20% gain is obtained. World first demonstration for a stable operation of GasPMT with bi-alkarine photocathode

Silicon tracker

Impact parameter resolution ILD BelleATLAS Alice SLD somehow achieved 20 years ago! (JB)

LHC detectors are beautiful…...but LHC Mega trackers A bit heavy !? Somewhat heavy !

Material budget is a key word Typical LHC hybrid pixel detector

Belle lightweight Silicon strip ladder flex r-z short (layer 1) Design: KEK Jigs: Melbourne Assembly:Princeton TPG Hybrid: Princeton High density Flex:Niigata Two layer flex:Princeton

Monolithic CMOS sensorCAP3: CAP4 revision Hawaii (Tested in the KEK-PS )

SOI pixel comes next Promising vertex detector for future collider experiment Excellent X-ray detector for the next generation…

SOI collaboration in US-JPN Slide presented at PIXEL2010 by the LBNL team

MPW (Multi Project Wafer) run ~Twice per Year 16

17 Integration Type Pixel (INTPIX4) 15 mm 10 mm 17x17  m, 512x832 (~430k ） pixels 、 13 Analog Out 、 CDS circuit in each pixel. Largest Chip so far. KEK 17

FNAL

LBNL Prototype Monolithic CMOS Imagers AMS 0.35  m-OPTO LDRD-1 (2005) 10, 20, 40  m 3T pixels LDRD-2 (2006) (+ LDRD-2RH(2007)) 20  m pixels,in-pixel CDS (+ RadHard pixels) OKI 0.15  m FD-SOI LDRD-SOI-1 (2007) 10  m pixels, analog & binary pixels OKI 0.20  m FD-SOI LDRD-SOI-2 (2008) 20  m pixels, in pixel CDS fast binary pixels LDRD-3 (2007) 20  m pixels, in-pixel CDS on-chip 5-bit ADCs SOImager (2009) ~13  m pixels, 4x4 mm 2 imager w/ fast readout TEAM Imager (2009) 1k x 1k 9  m pixels, analog Thin CMOS SOI

We should collaborate … R&D cost of advanced  -electronics is too much even for world major institutes. Design/test facility are expensive to maintain Persons capable of the task are very precious but few in the field. Share the access to special/expensive resources/ companies Mutual review/information exchange/training would be very helpful. Easier access to the chips developed by others.

More Functions in a finer pixel Physical limitations Huge R&D cost  Moor’s law seems saturate with 2D (planer) LSI only

22 T-micro + OKI Semi + KEK/LBNL Vertical (3D) Integration Further integration with  -bump bonding (~5 um pitch) technology of T- Micro(ZyCube)

Detector R&D summary Collaborations among US-J have been very fruitful for the last decade. It should be much more important for the next decades because the applications of the most advanced industrial-level technology to the detector is almost impossible for any single institute/country to realize.

24 Biggest issue in SOI Pixl Front Gate and Back Gate can couple each other Back Gate Effect Front Gate and Back Gate can couple each other Back Gate Effect Snsor and electronics are too close

Suppress the back gate effect. Shrink pixel size without loosing sensitive area. Increase break down voltage with low dose region. Less electric field in the BOX which may improve radiation hardness. Suppress the back gate effect. Shrink pixel size without loosing sensitive area. Increase break down voltage with low dose region. Less electric field in the BOX which may improve radiation hardness. Cut Top Si and BOX High Dose Cut Top Si and BOX High Dose Keep Top Si not affected Low Dose Keep Top Si not affected Low Dose 対策 : Buried p-Well (BPW) 25 BPW Implantation p(BPW)p+(PSUB) SOI Si Buried Oxide (BOX) PSUB Implantation PixelPeripheral (a) (b)

I ds -V gs Measurement without/with BPW 26 w/o BPW with BPW=0V NMOS Back gate effect is suppressed by the BPW. shift back channel open