Early PC Graphics Capabilities of the IBM Color Graphics Adapter (CGA) and Enhanced Graphics Adapter (EGA)

IBM product introductions MDA: introduced with IBM-PC in 1981 CGA: introduced as an option in 1982 EGA: introduced in 1984 (to replace CGA) VGA: introduced in 1987 (as PS/2 option)

CGA Engineered to coexist with IBM’s Monochrome Display Adapter (MDA), used for text display Designed to operate with Intel’s 8086/8088 CPU –MDA: max 32K VRAM: 0xB0000-0xB7FFF –CGA: max 32K VRAM: 0xB8000-0xBFFFF Designed to operate with Motorola’s 6845 CRTC –MDA: uses cpu’s i/o ports 0x3B4-0x3B5 –CGA: uses cpu’s i/o ports 0x3D4-0x3D5

The IBM design imperatives 1-MB 1) CGA shall work with 8086 CPU 8086 memory-addresses are 20-bits, so memory is restricted to 1 megabyte employs ‘segmented’ architecture that use 16-bit register-offsets 0xB0000 MDA 2) CGA shall coexist with the MDA The VRAM for IBM-PC’s Monochrome Display Adapter resides in a ‘reserved’ address-range starting from 0xB0000 Consequently: CGA’s VRAM starts at 0xB8000 and fits in a 32KB region

The imperatives (continued) 3) CGA shall use 6845 CRTC Motorola 6845 Cathode Ray Tube controller implemented only 7-bits for addressing display scan lines so could not address 200 rows in just one screen-refresh cycle Consequently: CGA’s VRAM shall be accessed in alternating ‘banks’ upper bank lower bank 0x0000 0x2000 Data for even-numbered scan lines Data for odd-numbered scan lines CGA VRAM

“Interlaced” VRAM addressing Even-numbered scanlines in lower bank: scanline 0: starts at offset 0 scanline 2: starts at offset 80 scanline 4: starts at offset 160 Odd-numbered scanlines in upper bank: scanline 1: starts at offset 0x2000 scanline 3: starts at offset 0x Scanline 5: starts at offset 0x

CGA graphics capabilities Two graphics modes (2-color or 4-color) Both use “packed-pixel” memory-model –8 pixels-per-byte, or 4 pixels-per-byte Four 4-color palette choices: –black+cyan+red+white –black+cyan+violet+white –black+green+red+yellow –black+dark-gray+light-gray+white

CGA screen resolutions color: 320x200 (4 packed pixels-per-byte) memory: 320x200/4 = bytes mono: 640x200 (8 packed pixels-per-byte) memory: 640x200/8 = bytes

Pixel-drawing Algorithm (mono) void draw_pixel_1( int x, int y, int color ) { intlocn = 0x2000*(y%2) + 80*(y/2) + (x/8); intmask = (1 > (x%8); unsigned chartemp = vram[ locn ]; color &= 1; color > (x%8); temp &= ~mask; temp |= color; vram[ locn ] = temp; }

void draw_pixel_2( int x, int y, int color ) { intlocn = 0x2000*(y%2) + 80*(y/2) + (2*x/8); intmask = (3 > (2*x%8); unsigned chartemp = vram[ locn ]; color &= 3; color > (2*x%8); temp &= ~mask; temp |= color; vram[ locn ] = temp; } Pixel-drawing Algorithm (color)

CGA pixels aren’t square Physical screen has 4:3 aspect-ratio CGA visual screen-resolutions: –color screen is 320x200 (ratio is 8:5) –b&w screen is 640x200 (ratio is 16:5) Physical square would be: –4-color mode: 240 wide by 200 high –2-color mode: 480 wide by 200 high So logical pixels are “stretched” vertically

Enhanced Graphics Adapter (EGA) Backward compatibility with the CGA Plus four additional display modes Higher graphics resolutions Greater color depths (16-colors) Faster screen refresh rates Needed to support more video memory Simplify video memory-byte addressing Needed additional “controller” hardware

EGA display modes New display modes 13, 14, 15, 16 13: 320x200 with 16-colors 14: 640x200 with 16-colors 15: 640x350 2-colors (monochrome) 16: 640x350 4-colors w/64K vram or 16-colors w/128K vram But uses “planar” memory organization, so relies on “Graphics Controller” hardware

Four memory “planes” Each CPU byte-address controls 8 pixels CPU addresses bytes in 4 parallel planes

Graphics Controller registers 0: Set/Reset register 1: Enable Set/Reset register 2: Color Compare register 3: Data-Rotate/Function-Select 4: Read Map Select register 5: Mode register 6: Miscellaneous register 7: Color Don’t Care register 8: Bit Mask register

Addressing device-registers Nine Graphics Controller registers (8-bits) Two ‘read’ modes, and four ‘write’ modes Multiplexed i/o addressing scheme: - register index is written to i/o port 0x3CE - register value is accessed via port 0x3CF CPU allows a pair of bytes to be written to adjacent port-addresses in one instruction

Reading a byte from VRAM Select which memory-plane Perform CPU read-byte instruction movb vram(%esi), %al Bytes from all four planes are copied to Graphics Controller’s Latches (32-bits) But only selected plane’s byte goes to AL

Read operation illustrated Controller’s Latch register plane 0 plane 1plane 2plane 3 2 Controller’s Read Map Select register CPU register AL

Writing a byte to VRAM Four distinct write modes (must choose) We illustrate Write Mode 0 (“Direct Write”) Four graphics controller registers involved: index 0: Set/Reset register index 1: Enable Set/Reset register index 3: Data-Rotate/Function-Select index 8: Bit Mask register

Steps for Write Mode 0 The new “fill color” goes into Set/Reset Set Enable Set/Reset to enable all planes Zero goes in Data-Rotate/Function-Select Setup Bit Mask for the pixel(s) to modify After these setup steps: –CPU reads from VRAM (to load the latches) –CPU writes to VRAM (to modify the pixel(s))

Set/Reset (index 0) The new fill-color Value (range is 0..15) outb( 0, 0x3CE ); // select Set/Reset register outb( color, 0x3CF ); // output the color-value Alternative programming (in one-step) outw( (color<<8)|0, 0x3CE );

Enable Set/Reset 0 = plane is write-protected 1 = plane can be modified outb( 1, 0x3CE ); // select Enable Set/Reset outb( 0x0F, 0x3CF ); // output selection bits Alternative programming (in one-step) outw( 0x0F01, 0x3CE );

Data-Rotate (index 3) Data-Rotation Count 0 to 7 bits (to right) Function Select outb( 3, 0x3CE ); // select Data-Rotate register outb( 0x00, 0x3CF ); // output the register value Alternative programming (in one-step) outw( 0x0003, 0x3CE ); Functions: 00=copy, 01=AND, 10=OR, 11=XOR (with Latch contents)

Bit Mask (index 8) The corresponding pixel will be modified (=1) or unmodified (=0) outb( 8, 0x3CE ); // select the Bit Mask register outb( mask, 0x3CF ); // output the register value Alternative programming (in one-step) outw( (mask<<8)|3, 0x3CE );

Write Mode 0 illustrated VRAM: Latch Register Bit Mask Fill-Color Set/Reset VRAM:

The EGA’s 16-color palette “planar” vram 4-bits Display screen A 4-bit pixel-value from planar vram selects a color from the palette to draw onto the display screen Color palette (16 colors)

Video Graphics Array (VGA) Offers both CGA and EGA emulation And supports three new display modes: mode 17: improved monochrome graphics mode 18: 16-colors using “square” pixels mode 19: supports 256 colors (8 bits/pixel) Provides faster display-refresh rates Supports analog multisync monitors

Class Demos ‘cgademo.cpp’ (4-color and b&w modes) ‘egademo.cpp’ (shows 16-color palette) ‘vgademo.cpp’ (square-pixels/256 colors)

In-class exercise #1 Use the ROM-BIOS ‘writestring’ service to add an explanatory title to our ‘egademo’ and ‘vgademo’ demonstration-programs (similar to code in our ‘cgademo’ program) Details on register-usage for the INT-0x10 firmware services are documented online on the ‘Ralf Brown Interrupt-List’ website

In-class exercise #2 Our EGA and VGA demo-programs make use of graphics display-modes 16 and 19 –Mode 16: 320-by-200 (4-bpp) –Mode 19: 320-by-200 (8-bpp) These modes do not have “square” pixels, so the circles look like ovals (“stretched”) Can you add an extra view that “corrects” for the distorted pixel-shape? (as in CGA)