Consistent Placement of Macro-Blocks Using Floorplanning and Standard-Cell Placement Saurabh Adya Igor Markov (University of Michigan)

Outline Motivations for mixed-mode placement Previous Work Components of our flow –Fixed-outline floorplanning –Standard-Cell placement Mixed-mode placement flow New Benchmarks Results Conclusions

Motivation IP reuse : PD with large rectangular blocks Integrated partitioning, FP & placement –Older flows apply separate optimizations –New generation of fast (min-cut) placers enable an integrated approach Partitioner is part of the placer Shifted cutlines perform floorplanning However handling large macros by RB is difficult –Small macros can be handled by RB (not in our work) Capo, Dragon, Feng Shui, etc. – can’t place large macros w/o overlaps

Previous Work Continuous optimization techniques –Force directed approaches [Eisenmann, Johannes, DAC ‘98] : mixed-mode [Mo et. al, ICCAD ‘00] : macros only + congestion –Are good with a lot of white-space in design –Otherwise, designer must remove overlaps Combinatorial optimization techniques –Particularly promising on constrained designs –[Nag et. al, DATE ‘98]: macros only –This work: mixed-mode

Cadence-recommended Mixed-Mode Flow for SEDSM 1.SEDSM places blocks at the periphery 2.Designer manually removes overlaps 3.From now on, blocks are considered fixed 4.QPlace is called to place standard-cells Otherwise, as our experiments show, –Handling many large cells is not ideal in QPlace Next-gen Cadence mixed-mode layout tool –In  -testing –Preliminary results are good

SEDSM Output (not new gen!)

Our Proposed Flow (Outline) 1.Generate initial placement using an arbitrary, min-WL standard-cell placer 2.Generate a fixed-outline floorplanning instance by “physical clustering” 3.Remove overlaps and generate valid macro locations using a fixed-outline floorplanner 4.Place small cells using standard-cell placer with macros considered fixed  (details – later)

Component : 1 Fast min-cut std-cell placer (Capo) – [Caldwell, Kahng and Markov, DAC 2000] Algorithms used –Min-cut bisection, optimal end-case placers –Multi-level FM partitioning –Cut-lines allowed to move, adaptive part. toler. Yet, Capo does not handle large macros So on

Component : 2 Fixed-outline floorplanner (Parquet) –[Adya and Markov, ICCD 2001] Solves a constraint satisfaction problem while minimizing wirelength Uses enhanced local search during annealing to satisfy outline constraints y-span  x-span 

Floorplan “Slack” Slack for block A in x- or y- dimension –The distance that A can be moved in x- or y- dimension without increasing the x- or y- span “Critical” blocks have zero slack Critical blocks lie on critical paths: analogy w STA We want to move critical blocks to improve fplan F E D A B C Left Packing Right Packing x- slack for block A = x(A right ) – x(A left ) A C B D E F critical blocks

Fixed-outline FP’er Parquet (based on Simulated Annealing) S.A. x-violation y-violation current outline required outline   Restart S.A.

In This Work: Improvements to Parquet HPWL minimization –Local annealing objective = linear combination of area and wirelength –Additional moves designed to improve HPWL Handling soft blocks –X/Y slacks suggest changes to AR of a block –At regular intervals during annealing Sort blocks according to slacks Shape blocks as suggested by the slacks Try to greedily reshape every soft blocks

Mixed-mode Placement Flow (1) Find a tentative placement of macros –Shred macros into fake standard-cells –Connect sub-cells with fake wires (pics follow) –Place “shredded netlist’’ using Capo –Compute locs of macros as average locs of sub-cells (continued later)

Shredding Macro Cells Shred all macros into smaller sub-cells Determine location of macros by averaging locations of sub-cells Determine the prevailing orientation of each macro (Should work with many min-WL placers) VaVa VrVr Case: Orient Va Vr : N Va Vr : S Va Vr : W Va Vr : E …etc(4 more cases) End Case;

Shredding Macro Cells (cont) Some macros may have fixed orientation –We tie the corner sub-cells to the corners of layout –(fake wires tying shredded pieces must be stronger) Lemma: this works for min-HPWL placers –This does not work for quadratic placers (!) Orient = N Orient = W

Initial Placement

Mixed-mode Placement Flow (2) Find a tentative placement of macros –Shred macros into fake standard-cells –Connect sub-cells with fake wires –Place “shredded netlist’’ using Capo –Compute locs of macros as average locs of sub-cells Generate a FP instance with soft & hard blocks –Cluster neighboring standard cells into soft blocks (continued later)

Physical Clustering

Mixed-mode Placement Flow (3) Find a tentative placement of macros –Shred macros into fake standard-cells –Connect sub-cells with fake wires –Place “shredded netlist’’ using Capo –Compute locs of macros as average locs of sub-cells Generate a FP instance with soft & hard blocks –Cluster neighboring standard cells into soft blocks Remove overlaps by fixed-outline floorplanning (Parquet) (continued later)

Floorplanned Design

Mixed-mode Placement Flow Find a tentative placement of macros –Shred macros into fake standard-cells –Place “shredded netlist’’ using Capo –Connect sub-cells with fake wires –Compute locs of macros as average locs of sub-cells Generate a FP instance with soft & hard blocks –Cluster neighboring standard cells into soft blocks Remove overlaps by fixed-outline FP (Parquet) Place std. cells consistently with the macros –Fix macros at current locations –Replace all standard cells using Capo

Final Placement

New Benchmarks Derived from ISPD-98 (IBM) circuits –Original specs give cell areas, but not dimensions We assumed rowheight = 16 for standard cells –Large cells  macros with AR=1 (cf. Dragon BMs) Whitespace for each design is 15 % Fixed pads placed randomly (cf. Dragon BMs) Available at : – and through

Conclusions Mixed-mode placement increasingly important Our flow combines techniques from std-cell placement & fixed-outline floorplanning Results: commercial tools can be improved Source code publicly available through: – – Ongoing work –Congestion analysis –Multilevel hierarchical floorplanning

Acknowledgements Financial support from –Gigascale Silicon Research Center –IBM Technical support from