PCB Design for Accurate Gauging Assuring Accuracy and Improving EMI and ESD Performance Thomas Cosby Applications Engineer 24 October 2012

PCB Design for Accurate Gauging Issue: Battery packs are used in many different applications and almost every environmental condition imaginable. Computers Handheld devices Power tools Transportation They are also handled by untrained individuals who may not know that electronic components are susceptible to ESD damage. e.g kids and teenagers Action: The Gas Gauge and Cell Protection devices serve vital functions in managing the battery and protecting it from damage. The pack designer must take care to design the hardware to protect the pack in the conditions where it will be used. Commercial Industrial Medical Military Hot or Cold Arid or Wet 10/24/2012 2

Assuring Accuracy 10/24/2012

bq20z65 / bq20z45 Reference Schematic Charge/Discharge FETS 2nd Level Protector Gas Gauge Fuse Circuit SMBus Interface CC Filter Voltage Sense Filter Thermistors LED Indicators 10/24/2012 4

Separating High and Low Currents Pack Connector Gauge AFE Rsense Q1 Q2 - + Bad Layout Scheme Good Layout Scheme Gauge AFE Pack Connector Rsense Q1 Q2 - + Ground plane Majority of the above can be achieved by a smart component placement scheme I know we are limited by PCB form factor, cell tabs … Avoid high current under the gauge and AFE ICs Minimize high current loop area 10/24/2012 5

Cell Voltage Inputs Separate filters required for safety C14 sets the time delay for activation of the output after any cell exceeds the threshold voltage Time delay is calculated as td = 1.2V X DelayCap(uF) / 0.18uA. D11 and C29 stabilize IC during pack short circuit event R1-R5 100 ohms may be fusible type Insure that the top and bottom voltage sensing lines are as close to the battery terminals as possible. Avoid any errors from IR drop in the high current path. 10/24/2012

Coulomb Counter Circuit The circuit pattern should be symmetrical for minimum current offset and minimum noise pickup. Surround the differential input by ground shield. Connections from the sense resistor and 100 Ohm resistors should be shielded and the traces should be routed in parallel. The filter circuit should be placed close to the device. Ensure good Kelvin connections. Sense Resistor Ground Shield Filter Circuit 10/24/2012 7

Grounding The thick blue wire above is high current ground. All other grounds (thin blue) are low current Low current ground must be separated from high current ground Low current ground must be connected to high current ground at one location only - at the sense resistor Maximize the ground pattern and reduce its inductance Use a ground plane if possible 10/24/2012 8

AFE Decoupling Capacitor Wires on PCBs are not ideal connection. REG REG Layout A is ideal. With layout B, noise from PACK- jumps into GND before decoupling caps. NG. Layout C is better than layout B. GND PACK- Layout A REG REG ＲＥＧ ＲＥＧ GND GND PACK- PACK- Layout B Layout C 10/24/2012 9

ESD Protection 10/24/2012

x Battery Pack ESD Hit 8-15kV PACK+ BMU COMM 8-15kV PACK- BMU – Battery Management Unit PACK+ BMU COMM 8-15kV So the end result is: the protection FETs, or the BMU will be damaged PACK- Pin Exposure will get ESD Hit ESD damages Protection FETs and BMU 10/24/2012 11

Battery Pack ESD Protection – PACK+ 8-15kV C1 PACK+ C2 R1 R2 D R3 BMU COMM C3 PACK- Preferred diverting path for a ZAP to Pack +: Capacitors C1 & C2 Ensure caps can absorb 2.5 micro coulombs 10/24/2012 12

Battery Pack ESD Protection – PACK- 8-15kV C1 PACK+ C2 R1 R2 D R3 BMU COMM C3 PACK- Preferred diverting path for a ZAP to Pack-: Capacitors C1 & C2 10/24/2012 13

Battery Pack ESD Protection – Other 8-15kV R1 R2 R3 BMU COMM D Near Pack- C3 PACK- Preferred diverting path for a ZAP to COMM: R1, R2 and D 10/24/2012 14

Use Proper Grounding Wrong Right Avoid Inductive Voltage Drop V = L di/dt Right Low level ground systems must connect to a single point at the sense resistor 10/24/2012 15

Use Spark Gaps PACK- PACK+ Use a spark gap at the pack connector SMD SMC T PRES Spark gap on the right has been exposed to multiple ESD strikes. Use a spark gap at the pack connector Reduce Peak Voltage seen by the internal circuit (IC) Must be PCB external Layer Must be free of solder mask or other non-conductive coating A 10-mil (0.2 mm) gap has a voltage breakdown about 1500 volts 10/24/2012 16

Communications Line Protection 100 ohms keeps signal edges sharp, but zeners may not survive continuous short Insure that diodes returns to Pack – not to low current ground 10/24/2012 17

What is the Effective Frequency of ESD (IEC)? IEC Current Waveform Extremely fast current rise time, ~1nsec Followed by a longer, but lower-level current transient The initial transient is most deadly to the electronics Apply EFFT (Extremely Fast Fourier Transform), 1/(πtr), where tr is the rise time, to the IEC current waveform ESD event is a 300MHz phenomenon (1nsec rise time is equivalent to 318MHz) IEC system level spec is not designed for device level ESD withstand threshold determination. The set-up is intended to simulate the stresses to some specific pins that probably will be subjected to IEC system level stress. This is a critical result, because it establishes the bandwidth that we needs to set up the defense against! 10/24/2012 18

"TI Proprietary Information" First-order Equivalent IEC Circuit First order simulation: VCC is worse than BAT 1cm A rough model: a 10mil PCB trace of 1cm long (highly geometry-dependent!) The waveforms show the circuit response to the AC excitation at the PACK terminals as a function of frequency 4/15/2017 "TI Proprietary Information" 10/24/2012 19

Effects of PCB Trace Length Minimize trace lengths VCC Trace length: 1cm 5cm 10cm IEC frequency resonances What do you see from these three graphs? As the trace gets longer, multiple resonance peaks shift toward lower frequency; we have not even counted in the vias! 4/15/2017 "TI Proprietary Information" 10/24/2012 20

Paralleling Capacitance Paralleling additional small capacitors reduces high frequency gain But is it true that we should parallel as many as possible? 1uF 1uF//0.1uF 10/24/2012 21

"TI Proprietary Information" Will More Parallel Capacitance Help? 560pF 0.1uF 1uF 1uF 1uF sets the tone, 0.1uF lower the gain above 20MHz, and 560pF further reduces the gain at IEC frequency Attention should be paid to the resonance peak caused by paralleling capacitance "TI Proprietary Information" 1uF//0.1uF//560pF 10/24/2012 22

With a 10 ohm series resistor Will Adding Series Resistance Help? A 10 ohm resistor is added in series to the VCC Damps the resonance and reduces peak values No series resistor With a 10 ohm series resistor 10/24/2012 23

EMI Protection 10/24/2012

Electric Field Causing False Fuse Activation When SAFE is not activated, D2 is reverse biased and Q1 is OFF Turning on a 2W walkie-talkie (SX700R ) next to the circuit board can turn on Q1, falsely causing FUSE blow (462 MHz) SAFE OVP PFIN D2 bq20z90 VCC Q1 Chemical fuse C6 What is the root cause? How can we improve? This is a real example of EMI causing false fuse activation, At 462 MHz, ¼ Wavelength: 16 cm 1/20 Wavelength: 3.2 cm 10/24/2012 25

Improved Layouts: No False Fuse Blown under RF Long Trace Old layout Short Trace The old layout has a long trace from the SAFE pin of the IC to the diode D2, and the trace is not shielded by any ground copper, so it’s rectifying the high frequency energy into the cap C6, We went ahead and reved the board, in the new layout, the PCB trace from the IC’s Safe pin to D2 is less than 1 cm long, and it’s shielded by ground copper, it’s like shortening the antenna, and the false fuse-blow never appear again. Improved layout Shorten the antenna of the receiver 10/24/2012 26

Common Mode Issues 90% of EMI problems are caused by CM Current spreading to areas where it can couple into something which can Resonate and Radiate. All CM current comes from Intended Fields which are NOT properly contained!! “Ground” is often considered a region of zero voltage potential with zero resistance or impedance, but this is not true except at DC. 10/24/2012

EMI Control - Routing 10/24/2012

EMI Control – PCB Stackup Try to provide a good ground plane. 10/24/2012

bq40z50 Next Generation IT Battery Manager 10/24/2012

bq40z50 EVM Schematic 10/24/2012 31

bq40z50 EVM Layout Signal Plane GND Plane GND Plane Gas Gauge High Temp Section Power Stage Cell Inputs Top Layer 2nd Layer 3rd Layer Bottom Layer 10/24/2012 32

DISCHARGE CURRENT EXAMPLE bq40z50 EVM Layout Power Stage DISCHARGE CURRENT EXAMPLE Sense Resistor FET caps PACK- SYSPRES PACK+ VCC Resistor Spark gaps FETs (back side) 4P 3P 2P 1P 1N Top Layer 10/24/2012 33

bq40z50 EVM Layout Gas Gauge Thermistors LEDs (can add heat) Bq40z50 Discrete components (others on backside) Coulomb Counter Filter 2nd Level Protector Top Layer 10/24/2012 34

bq40z50 EVM Layout GND and Signal Planes Good GND Return via Layer 2 Kelvin Voltage Senses 2nd Layer 3rd Layer 10/24/2012 35

TI Confidential - NDA Restrictions Questions 4/15/2017 TI Confidential - NDA Restrictions