8255 I/O

Overview 68HC11 pulse accumulator example: The Egg-O-Matic More about the Intel 8255A Overview of the Motorola 68HC24

Pulse Accumulator Example: Egg- O-Matic We want a (nearly) perfect 3-minute egg Functional concept oMicrocontroller will turn a heating unit on (HEAT = 1) oTemperature sensor will detect boiling (BOIL = 1 when boiling) oMicrocontroller will turn heating unit off (HEAT = 0) Implementation concept oPulse accumulator will be used in “gated-time accumulation mode” oPulse accumulator will count (at E-clock/64) only when boiling (BOIL = 1) oAn interrupt service routine will execute when pulse accumulator overflows and will maintain a “big count” to count for 3 minutes Cont..

Pulse Accumulator Example: Egg- O-Matic

Egg-O-Matic initialization (1) Pulse accumulator control register (PACTL) oDDRA7 =1: PA7 (PAI) is input only oPAEN = 1: Pulse accumulator system enabled oPAMOD = 1, PAEDGE = 0: Zero on PAI inhibits counting Turn on interrupt oSet PAOVI bit in TMSK2 Turn on heat by setting PB0 CONTROL: EQU % ; PA control value PAOV: EQU % ; PA overflow mask (TFLAG2/TMSK2) NPAOV: EQU % ; Inverted PAOV mask HEATON: EQU % ; Heat on mask (in PORTB)

Egg-O-Matic initialization (2) Time values oPulse accumulator will increment every 64 E-clock periods, i.e. every 64´(500 ns) = 32 ms for a 2 MHz E Clock o250 increments gives 250´(32 ms) = 8 ms of time o22,500 overflows of 8 ms each gives 22500´(8 ms) = 180 s = 3 minutes Needed: oPreload PACNT to = 6 oMaintain a 16-bit down-counter in software, preload to 22,500 COUNT1: EQU !6 ; 250 gives 8 ms with 2MHz E clock COUNT2: EQU !22500 ; 22500*8ms = 3 mins

Egg-O-Matic: COOKEGG Subroutine ; Subroutine to start cooking the egg COOKEGG: LDD #COUNT2 ; Initialize big counter STD BIGCNTR CLR DONEFLAG ; Clear done flag (not done) LDAA #CONTROL ; Set PA control register STAA PACTL,X BCLR TFLG2,X,NPAOV ; Clear flag if set LDAA #COUNT1 ; Preload pulse accumulator STAA PACNT,X BSET TMSK2,X,PAOV ; Enable interrupt CLI BSET PORTB,X,HEATON ; Turn heater on RTS ; Continue with main program

Egg-O-Matic: PA_ISR interrupt service routine PA_ISR: LDX #REGBASE ; Register base address LDAA #COUNT1 ; Reload pulse accumulator STAA PACNT,X BCLR PACTL,X,PAOV ; Clear overflow flag DEC BIGCNTR ; Decrement big count BNE EXIT ; Exit if not done BCLR PORTB,X,HEATON ; Done. Turn off heat BCLR TMSK2,X,PAOV ; Turn off interrupt COM DONEFLAG ; Mark as done EXIT: RTI ; Return from interrupt

8255 Programmable Peripheral Interface (PPI) Different peripheral chips may be added to an expanded mode 68HC11 Consider the 8255A Programmable Peripheral Interface (PPI) oIntel peripheral family , MCS-51, 80x86 oProvides a set of programmable (parallel) I/O ports for use in a wide range of microprocessor systems and applications o24 programmable I/O pins  8-bit port A  8-bit port B  8-bit port C, split into two 4-bit halves oThree modes of operation  Basic input or output (mode 0) Cont..

8255 Programmable Peripheral Interface (PPI)  Strobed input or output (mode 1)  Bidirectional input-output (mode 2) oDirect bit set/reset (port C) oPackaged in a 40-pin DIP

8255A Block Diagram

8255A Pins Processor interface oD7-D0: Data bus to/from microprocessor oCS’: Chip select (active low) oRD’: Read enable (active low) oWR’: Write enable (active low) oA1, A0: Register address bits  00 = Port A  01 = Port B  10 = Port C  11 = Control Register (write only) oRESET: Chip reset Cont..

8255A Pins Ports oPA7-PA0 oPB7-PB0 oPC7-PC0 Power (VCC) and ground (GND)

8255A Modes Mode 0 oSimple input or output (unidirectional) operations oPorts A, B, and C can be programmed to be in Mode 0  Ports A and B programmed as all 8 bits  Port C split into high and low nibbles oOutputs are latched, inputs are not Mode 1 oStrobed input or output (handshaking) oPorts A and B can be used in Mode 1 oPins from Port C are “borrowed” for handshaking control signals  3 bits for Port A, 3 bits for Port B Cont..

8255A Modes  Control signals are “data ready,” “data receipt acknowledge,” “interrupt” Mode 2 o8-bit bidirectional input/output with handshaking oOnly Port A can be used in Mode 2 oFive Port C pins are used for the handshaking and interrupt request lines oPort B can be concurrently operated in Modes 0 or 1 (with use of PC0-2)

8255A control word Ports are configured by writing a byte to the Control Register oBit 7 = 1 to select configuration operation

8255A Port C Set/Reset Individual bits in Port C can also be set (to 1) or reset (to 0) oControl word value indicates bit position and set or reset oBit 7 = 0 to select set/reset operation

8255A Mode 0 example: Hardware 8255 is memory mapped at $7F00-$7F03 ($7F00- $7FFF used) Port A is input, Port C (low) is output

8255 Mode 0 example: Initialization PORTA: EQU $7F00 PORTB: EQU $7F01 PORTC: EQU $7F02 CONTROL: EQU $7F03 INIT0: LDAA #$90 ; Write control word STAA CONTROL RTS ; Done

8255A Mode 0 example: Set/Reset Use the set/reset feature of Port C ; Set Bit ; Input: Bit location in low 3 bits of ACCA ; Changed: ACCA SETBIT: ANDA #$03 ; Mask other bits LSLA ; Put in Bit Select field ORA #$01 ; Set S/R bit STAA CONTROL ; Write to control register RTS ; Done

8255A Mode 1 Configuration

8255A Mode 1 Input Timing

8255A Mode 1 Output Timing

8255A Mode 1 Status Mode 1 status is available in the Port C register oRead Port C to read status oAvailable only if in Mode 1 Input configuration: (Fig-1) Output configuration: (Fig-2)

8255A Mode 2 Mode 2 allows bidirectional input/output on Port A oHandshaking oProtocol to determine whether 8255A or external peripheral can drive the shared data lines (PA7-PA0) Control signals oSTB’: Strobe (input) oIBF: Input buffer full (output) oOBF’: Output buffer full (output) oACK’: Acknowledge (input) oINTR: Interrupt

8255A Mode 2 Configuration

8255A Mode 2 Timing

8255A Mode 2 Status Mode 2 status bits are available by reading Port C (Figure) Group B bits determined by Port B configuration

68HC24 Port Replacement Unit (PRU) Replaces Port B and Port C I/O functions “lost” when using expanded mode oPRU’s register set matches the 68HC11 registers for Port B and Port C for control, status, and data oRegular expanded mode bus cycles are used to access the PRU Primary application is development systems oFinal design can use on-chip 68HC11 ports and memory oThere are often cheaper ways to implement specific I/O functions needed for an expanded mode system 44-pin PLCC or 40-pin DIP package

Single-chip Mode/Expanded Mode compatibility Addressing oPort B and Port C register addresses are treated as external memory by the 68HC11 when it is in expanded mode oPRU registers are accessed at memory addresses defined for replaced onchip registers oPRU supports register address space re-mapping like the 68HC11 Interrupts oIRQ’ interrupt line is asserted by PRU for Port B and C interrup ts oIRQ’ uses the same vector as the handshake and strobed I/O interrupts There are some subtle (minor) timing differences oInternal clock signals are not available in the PRU oSTRB signals occur slightly later

PRU Interfacing