Run Time Monitoring of Reactive System Models Mikhail Auguston Naval Postgraduate School Mark Trakhtenbrot Holon Academic Institute of.

Slides:



Advertisements
Similar presentations
1 Verification by Model Checking. 2 Part 1 : Motivation.
Advertisements

The Quest for Correctness Joseph Sifakis VERIMAG Laboratory 2nd Sogeti Testing Academy April 29th 2009.
Model Checking Lecture 2. Three important decisions when choosing system properties: 1automata vs. logic 2branching vs. linear time 3safety vs. liveness.
Modeling Software Systems Lecture 2 Book: Chapter 4.
Auto-Generation of Test Cases for Infinite States Reactive Systems Based on Symbolic Execution and Formula Rewriting Donghuo Chen School of Computer Science.
CS 267: Automated Verification Lecture 8: Automata Theoretic Model Checking Instructor: Tevfik Bultan.
Automatic Verification Book: Chapter 6. What is verification? Traditionally, verification means proof of correctness automatic: model checking deductive:
Budapest University of Technology and EconomicsDagstuhl 2004 Department of Measurement and Information Systems 1 Towards Automated Formal Verification.
ECE Synthesis & Verification - L271 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Systems Model Checking basics.
Temporal Logic and the NuSMV Model Checker CS 680 Formal Methods Jeremy Johnson.
CS6133 Software Specification and Verification
STATEMATE A Working Environment for the Development of Complex Reactive Systems.
Implementation Oriented Mutation Testing of Statechart Models Mark Trakhtenbrot Holon Institute of Technology
Presented by: Thabet Kacem Spring Outline Contributions Introduction Proposed Approach Related Work Reconception of ADLs XTEAM Tool Chain Discussion.
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
Run Time Monitoring of Reactive Systems Mikhail Auguston Naval Postgraduate School Mark Trakhtenbrot Holon Academic Institute of Technology.
ISBN Chapter 3 Describing Syntax and Semantics.
Formal Methods in Software Engineering Credit Hours: 3+0 By: Qaisar Javaid Assistant Professor Formal Methods in Software Engineering1.
Establishing IV&V Properties Steve Raque, NASA IV&V Facility Dr. Doron Drusinsky, Naval Postgraduate School 9/4/20091Establishing IV&V Properties.
Spin Tutorial (some verification options). Assertion is always executable and has no other effect on the state of the system than to change the local.
Logic Based LSC Consistency Testing Presenter: Anup Niroula.
Temporal Specification Chris Patel Vinay Viswanathan.
Use of Verification for Testing and Debugging of Complex Reactive Systems Mark Trakhtenbrot Holon Academic Institute of Technology.
Model Checking. Used in studying behaviors of reactive systems Typically involves three steps: Create a finite state model (FSM) of the system design.
Lecture 4&5: Model Checking: A quick introduction Professor Aditya Ghose Director, Decision Systems Lab School of IT and Computer Science University of.
ECE Synthesis & Verification1 ECE 667 Spring 2011 Synthesis and Verification of Digital Systems Verification Introduction.
Specification Formalisms Book: Chapter 5. Properties of formalisms Formal. Unique interpretation. Intuitive. Simple to understand (visual). Succinct.
Embedded Systems Laboratory Department of Computer and Information Science Linköping University Sweden Formal Verification and Model Checking Traian Pop.
A logic for reasoning about digital rights Riccardo Pucella, Vicky Weissman Cornell University.
ESE601: Hybrid Systems Introduction to verification Spring 2006.
Describing Syntax and Semantics
School of Computer ScienceG53FSP Formal Specification1 Dr. Rong Qu Introduction to Formal Specification
Lecture 6 Template Semantics CS6133 Fall 2011 Software Specification and Verification.
02/06/05 “Investigating a Finite–State Machine Notation for Discrete–Event Systems” Nikolay Stoimenov.
Verification technique on SA applications using Incremental Model Checking 컴퓨터학과 신영주.
A Visual Interactive Tool For the Course “Automata and Formal Languages” Holon Institute of Technology Mark Trakhtenbrot, Vladimir Nodelman, Avi Lamai.
Institute for Applied Information Processing and Communications 1 Karin Greimel Semmering, Open Implication.
Roza Ghamari Bogazici University April Outline Introduction SystemC Language Formal Verification Techniques for SystemC Design and Verification.
Using Mathematica for modeling, simulation and property checking of hardware systems Ghiath AL SAMMANE VDS group : Verification & Modeling of Digital systems.
Model Based Conformance Testing for Extensible Internet Protocols Anastasia Tugaenko Scientific Adviser: Nikolay Pakulin, PhD.
Benjamin Gamble. What is Time?  Can mean many different things to a computer Dynamic Equation Variable System State 2.
5/27/03MDES Supporting Model-Based Validation at Run-time Insup Lee and Oleg Sokolsky Department of Computer and Information Science University of.
Formal Verification Lecture 9. Formal Verification Formal verification relies on Descriptions of the properties or requirements Descriptions of systems.
A Static Approach to Consistency Verification of UML Models Andrea Baruzzo Department of Computer Science University of Udine MoDeV.
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
Simulation is the process of studying the behavior of a real system by using a model that replicates the behavior of the system under different scenarios.
1 Qualitative Reasoning of Distributed Object Design Nima Kaveh & Wolfgang Emmerich Software Systems Engineering Dept. Computer Science University College.
Safety-Critical Systems 5 Testing and V&V T
1 CSEP590 – Model Checking and Automated Verification Lecture outline for August 6, 2003.
Verification & Validation By: Amir Masoud Gharehbaghi
VIS Technology Transfer Course Session 7 Fairness Constraints and Monitors Serdar Tasiran.
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
Dimensions of Formal Verification and Validation Doron Drusinsky Bret Michael Mantak Shing Naval Postgraduate School.
Copyright 2001, Matt Dwyer, John Hatcliff, and Radu Iosif. The syllabus and all lectures for this course are copyrighted materials and may not be used.
Theory-Aided Model Checking of Concurrent Transition Systems Guy Katz, Clark Barrett, David Harel New York University Weizmann Institute of Science.
1 Temporal logic. 2 Prop. logic: model and reason about static situations. Example: Are there truth values that can be assigned to x,y simultaneously.
Software Systems Verification and Validation Laboratory Assignment 4 Model checking Assignment date: Lab 4 Delivery date: Lab 4, 5.
From Natural Language to LTL: Difficulties Capturing Natural Language Specification in Formal Languages for Automatic Analysis Elsa L Gunter NJIT.
MOPS: an Infrastructure for Examining Security Properties of Software Authors Hao Chen and David Wagner Appears in ACM Conference on Computer and Communications.
6/12/20161 a.a.2015/2016 Prof. Anna Labella Formal Methods in software development.
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
Model Checking Early Requirements Specifications in Tropos Presented by Chin-Yi Tsai.
Formally Specified Monitoring of Temporal Properties
Program Synthesis is a Game
Software Design Methodology
CSCI1600: Embedded and Real Time Software
ECE-C662 Introduction to Behavioral Synthesis Knapp Text Ch
CSCI1600: Embedded and Real Time Software
Introduction to verification
Presentation transcript:

Run Time Monitoring of Reactive System Models Mikhail Auguston Naval Postgraduate School Mark Trakhtenbrot Holon Academic Institute of Technology

Outline Problems in development of reactive systems Model-based development and analysis Our approach:  TL-based assertion language  Automatic generation of monitors for run-time verification Outline of translation scheme Further steps

Why development of reactive systems is difficult? Main problem: complex behavior  Intricate event-driven interaction with the environment  Concurrency and timing factors Typically:  Critical applications (embedded RT controllers, …)  Must fulfill tough reqs (safety, timeliness, … ) Challenges:  Capture reqs; design; check that system meets its spec

So, what to do? Apply formal methods! Precise spec of behavior:  TL [Pnueli, …] (future/past modalities: LTL; timing: MTL)  templates for typical properties [Avrunin, …] (response, precedence, existence, absence,…) Model-based development:  formal model of system (behavior, structure, …)  Harel statecharts to capture behavior; a renown standard  executable model; a basis for automated tools  model-level analysis (closer to problem domain)

Example: Early Warning System

Model-based analysis with Statemate Simulation: check, record and replay test scenarios Verification: based on predefined assertion templates Code synthesis: executable C, for host or target OS Watchdog charts for execution monitoring: - co-executed with the system model - property violation: entering into ERROR state

Sample monitor chart Assertion: Processing of a request must be accomplished - within 5 seconds - before receiving the next request WaitProcessError Request Processing Done Request or Timeout(5) /Violation Notification

Our approach: Statemate-based run-time verification Main new features:  TL-based assertion language to spec behavior  Automatic creation of monitor charts from assertions Used Statemate capabilities:  Co-translation of model and monitors to C  Monitoring of code execution

Advantages of the approach Flexible assertion language vs. predefined patterns Smooth transition: assertions  executable monitors Overcome limitations of simulation and verification

 Analyze models reflecting design decisions (tasks/events mapping,…), in realistic target environment  Real time analysis - rather than SIM time SIM synch time (clock-driven systems): all reactions assume same duration SIM asynch time (event-driven systems): all reactions assume zero duration  No "finite state" limitation may connect to real input sources

Assertion language  Boolean expressions: system state properties in(S) and (x > 5) ; entered(S)  started(A) ; ch(d)  Regular expressions: describe sequences of states [SELECT (Open | Read | Write | Close) FROM execution] SATISFY Open (Read | Write )* Close  Temporal formulas: order properties ALWAYS (request  EVENTUALLY response) ALWAYS (execute  SOMETIME_WAS do_set_up)  Timed temporal formulas: real-time restrictions ALWAYS (request  EVENTUALLY (10) response)  Actions: to trace interesting events (e.g. property violation) reports, profiling info (based on objects’ attributes)

More on TL formula classification Basic formula: no temporal operators Restricted formula: EVENTUALLY(15) (ALWAYS(30) p) ALWAYS(30) (p  EVENTUALLY(15) q) Unrestricted formula:  nesting depth <= 2 for unrestricted future operators (following Manna&Pnueli for LTL)  unrestricted operator not embedded in a restricted one

Semantic issues  Monitoring: deals with finite runs; semantics of TL – based on infinite runs  [Eisner, et.al.]: reasoning on truncated executions  We follow the neutral view  Assume the run finishes 4 sec after the last p ALWAYS (p  EVENTUALLY(10) q) ; false if no q after the last p ALWAYS (p  ALWAYS(10) q) ; true if always q after the last p  In general: user responsible to provide proper actions

Example - assertion for EWS ALWAYS (OUT_OF_RANGE  EVENTUALLY (15) (RESET or started(PRINT_ALARM))) ON_FAIL [printf(“Violation after occurrence of OUT_OF_RANGE at time %f “, OUT_OF_RANGE.occur_time)]

Sample monitor construction ALWAYS (OUT_OF_RANGE  EVENTUALLY (15) (RESET or started(PRINT_ALARM))) / ERROR_MESSAGE

Translation of restricted formula ALWAYS (N) P

Translation of unrestricted formula ALWAYS (P)

Further steps Implementation:  done - experiments with manually created monitors  next step – actual implementation A more friendly assertion language  e.g. combine English with formulas Optimized translation for certain types of assertions Apply to other design paradigms using statecharts  e.g. in OO: monitor systems with dynamically created objects (problematic for model checking)

Run Time Monitoring of Reactive System Models Thanks for your attention

More on temporal properties Manna & Pnueli Classification (P – past formula) :  Safety: ALWAYS (P), Guarantee: EVENTUALLY (P)  Obligation: Boolean combination of safety & guarantee  Response: ALWAYS (EVENTUALLY(P))  Persistence: EVENTUALLY (ALWAYS(P))  Reactivity: Bool. combination of response & persistence  Any TL formula is equivalent to a Reactivity formula Limitations:  nesting depth <= 2 for unrestricted future operators  unrestricted operator not embedded in a restricted one