1 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) ECpE 583 Reconfigurable Computing Lect 5: Tues 9/9/2008 (State Machines: Part 2) Instructor: Dr. Phillip Jones Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA (coming soon) (temporary)

2 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) Class videos available (WebCT) Staff still working on installing Xilinx Hardware development tools Updated schedule Suggested readings: –FSM “good practices” paper (Note: in Verilog) – The Fundamentals of Efficient Synthesizable Finite State Machine (2002)The Fundamentals of Efficient Synthesizable Finite State Machine Synthesizable Finite State Machine Design Techniques (2003)Synthesizable Finite State Machine Design Techniques –Models of computation paper Design Patterns for Reconfigurable Computing – Class Announcements

3 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) Revisit some concepts from last lecture Continue State Machine Design Outline

4 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) VHDL: Sequential Statements In a process –Typically when dealing with variables – Signals are updated in parallel (concurrently)

5 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) VHDL: Synthesizable vs. Non-Synthesizable Examples of non-synthesizable constructs –Code that specifies delays wait for 2ns –File operations Tools give error messages??

6 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) Finite State Machines What types of applications are they well suited –Streaming pattern recognition –Sequential event based control logic Allow hardware designer to reason about things in small pieces

7 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) Alert!! Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM Send Alert !nroClengthdest port

8 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) Moore and Mealy FSMs Moore: Output is only a function of the current state Mealy: Output is a function of the current state and input (“Mealy is more”) –That is more things determine the output –Same computational power as Moore Any Mealy machine has an equivalent Moore –Mealy can make better use of resources

9 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) Moore FSM Moore: Output is only a function of the current state Example detect every occurrence of “1010” Start (0) 0 (0) (0) (0) (1)

10 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) Moore FSM Moore: Output is only a function of the current state Example: vending machine –Events (assume all items cost 1 coin): Insert Coin Make selection Start (0) Coin (0) Insert Coin Snack (1) Make selection Insert Coin Make selection Return (0) Insert Coin Make selection

11 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) Moore FSM Moore: Output is only a function of the current state Example: vending machine –Events (assume all items cost 1 coin): Insert Coin Make selection Return Coin Start (0) Coin (0) Insert Coin Snack (1) Make selection Insert Coin Make selection Return (0) Return Coin

12 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) Moore FSM Moore: Output is only a function of the current state Example: vending machine –Events (assume all items cost 1 coin): Insert Coin Make selection Return Coin Start (0) Coin (0) Insert Coin Snack (1) Make selection Insert Coin Make selection Return (0) Return Coin Make selection Return coin Insert Coin Return Coin

13 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) Moore FSM Moore: Output is only a function of the current state Example: vending machine –Events (assume all items cost 1 coin): Insert Coin Make selection Start (0) Coin (0) Insert Coin Snack (1) Make selection Insert Coin Make selection Return (0) Insert Coin Make selection Make Coin a snack option

14 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) Mealy FSM Moore: Output a function of the current state, and input Example detect every occurrence of “1011” State Name

15 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) Mealy FSM 1/0 0/ Input output Moore: Output a function of the current state, and input Example detect every occurrence of “1011” Start

16 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) Mealy FSM 1/0 0/ Mealy: Output a function of the current state, and input Example detect every occurrence of “1011” 1/0 0/0 1/1 0/0 Start 1/0

17 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) Let: –X be inputs –Z be outputs –State(t) be the state of the FSM at the current time –State(t+1) be the next state of the FSM –δ be the transition between states State(t+1) = δ(State(t), X) Output –Moore: Z(State(t)) –Mealy: Z(State(t), X) FSM: General Circuit Architecture x=1/z=0 0/1 S1S2 1/0 0/0 z=0

18 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) FSM: General Circuit Architecture Combinational Logic Inputs: X Z(State(t)) Z(State(t),X) Outputs Moore Mealy State Storage DFF State(t) State(t+1) = δ(State(t), X) Next State

19 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) VHDL: IF and CASE constructs IF THEN ELSE can be mapped to a 2:1 Multiplexer (Mux) 2:1 Mux sel = b“0” x”C” x”D” in_0 in_1 x”C” IF (sel = ‘0’) THEN out_1 <= in_0; ELSE out_1 <= in_1 END IF; out_1

20 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) VHDL: IF and CASE constructs 4:1 Mux sel = b“10” x”C” x”D” x”2” x”7” in_0 in_1 in_2 in_3 x”7” Mapping a CASE statement to a 4:1 Mux out_1 CASE sel is WHEN “00” => out_1 <= in_0; WHEN “01” => out_1 <= in_1; WHEN “10” => out_1 <= in_2; WHEN “11” => out_1 <= in_3 WHEN OTHERS => out_1 <= in_0; END CASE; Why do we need others here?

21 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) CASE state is WHEN state_1 => IF (sel = ‘0’) THEN mux_out <= ‘1’; ELSE mux_out <= ‘0’; END IF; WHEN state_11 => -- similar code WHEN state_011 => IF (sel = ‘0’) THEN mux_out <= ‘0’; ELSE mux_out <= ‘1’; WHEN state_1011 => --similar code END CASE; VHDL: IF and CASE constructs State = {state_1, state_11, state_011, state_1011} = {“00”, ”01”, ”10”, ”11”} Enumerated Type Mapping a CASE statement to a 1:4 Decoder 1:4 Decoder 2 out_0 out_1 out_2 out_3 state “10” on 2:1 Mux off 2:1 Mux off 2:1 Mux off 2:1 Mux

22 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) CASE state is WHEN state_1 => IF (sel = ‘0’) THEN mux_out <= ‘1’; ELSE mux_out <= ‘0’; END IF; WHEN state_11 => -- similar code WHEN state_011 => IF (sel = ‘0’) THEN mux_out <= ‘0’; ELSE mux_out <= ‘1’; WHEN state_1011 => --similar code END CASE; VHDL: IF and CASE constructs State = {state_1, state_11, state_011, state_1011} = {“00”, ”01”, ”10”, ”11”} Enumerated Type Mapping a CASE statement to a 1:4 Decoder 1:4 Decoder 2 out_0 out_1 out_2 out_3 state “00” on 2:1 Mux off 2:1 Mux off 2:1 Mux off 2:1 Mux

23 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) FSM: General Circuit Architecture Combinational Logic Inputs: X Z(State(t)) Z(State(t),X) Outputs Moore Mealy State Storage DFF State(t) State(t+1) = δ(State(t), X) Next State

24 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) -- Store the “state” Update_State: process(clk) begin if(clk’event and clk=‘1’) then state <= next_state; end if; end process Update_State; VHDL for Mealy (“1011”) Example DFF next_state state

25 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) -- Compute combinational logic Combinational: process(x, state) begin case state is when state_1 => if(x = ‘0’) then z <= ‘0‘; next_state <= state_1; else z <= ‘0‘; next_state <= state_11; end if; when state_11 => if(x = ‘0’) then z <= ‘0’; next_state <= state_1; else z <= ‘0‘; next_state <= state_011 ; end if; VHDL for Mealy (“1011”) Example 1/0 0/ /0 0/0 1/1 0/0 Start 1/0 Compute output Compute next_state

26 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) when state_011 => if(x = ‘0’) then z <= ‘0‘; next_state <= state_1011; else z <= ‘0‘; next_state <= state_011; end if; when state_1011 => if(x = ‘0’) then z <= ‘0’; next_state <= state_1; else z <= ‘1‘; next_state <= state_11; end if; end case; end process Combinational; VHDL for Mealy (“1011”) Example 1/ /0 0/0 1/1 0/0 1/0

27 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) Show using Xilinx ISE tools (Note: first open project from scratch) Simulation of Mealy (“1011”) Example

28 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) Next Lecture UDP Network Processing example Modular and Hierarchical Design Mapping Logic to FPGAs Remote MP0 Demo

29 - ECpE 583 (Reconfigurable Computing): State Machines (Part 2) Iowa State University (Ames) Questions/Comments/Concerns Write down –Main point of lecture –One thing that’s still not quite clear –If everything is clear, then give an example of how to apply something from lecture OR