Multi-Project Reticle Floorplanning and Wafer Dicing Andrew B. Kahng 1 Ion I. Mandoiu 2 Qinke Wang 1 Xu Xu 1 Alex Zelikovsky 3 (1) CSE Department, University of California at San Diego (2) CSE Department, University of Connecticut (3) CS Department, Georgia State University

Introduction to Multi-Project Wafer Outline Side-to-side wafer dicing problem Reticle floorplanning and wafer dicing problem Conclusions and future research directions Experimental results Design flow

Mask and Wafer Cost Mask cost: $1M for 90 nm technology Wafer cost: $4K per wafer

Introduction to Multi-Project Wafer Share rising costs of mask tooling between multiple prototype and low production volume designs  Multi-Project Wafer Image courtesy of CMP and EuroPractice

History of Multi-Project Wafer Introduced in late 1970s and early 1980s Companies: MOSIS, CMP, TSMC Several approaches proposed Chen et al. give bottom-left fill algorithm, 2003 Anderson et al. proposed grid packing algorithm, 2003 Tools: MaskCompose, GTMuch

Introduction to Multi-Project Wafer Outline Side-to-side wafer dicing problem Reticle floorplanning and wafer dicing problem Conclusions and future research directions Experimental results Design flow

Design Flow  Unique designs

Design Flow  Custom designs  Partition between reticles

Design Flow  Custom designs  Partition between shuttles  Reticle placement

Design Flow  Custom designs  Partition between shuttles  Reticle placement  Stepper shot-map print shot-map

Design Flow  Custom designs  Partition between shuttles  Reticle placement  Stepper shot-map  Dicing plan design

Design Flow  Custom designs  Partition between shuttles  Reticle placement  Stepper shot-map  Dicing plan design

Design Flow  Custom designs  Partition between shuttles  Reticle placement  Stepper shot-map  Dicing plan design  Extract dice

Introduction to Multi-Project Wafer Outline Side-to-side wafer dicing problem Reticle floorplanning and wafer dicing problem Conclusions and future research directions Experimental results Design flow

Why Dicing a Problem? Sliced out A die is sliced out if and only if: - Four edges are on the cut lines - No cut lines pass through the die Dicing is easy for standard wafers. All dice will be sliced out. Dicing is complex for MPW. Most dice will be destroyed if placement is not well aligned. Side-to-side dicing is the prevalent wafer dicing technology

Side-to-side Dicing Problem Given: reticle placement wafer shot-map required volume for each die Find: Set of horizontal and vertical cut lines (dicing plan) To Minimize: w = # wafers used

H-Conflict dice are in H-Conflict if they can not be sliced out horizontally and 2 are in H-conflict Die 1 is in H-Conflict with entire row of Die

Horizontal Dicing Plan A horizontal Dicing Plan (DP) is a set of lines which dice one row of prints A set of dice which are pairwise not in H-conflict can be sliced out by a DP We seek such maximal horizontal independent sets MHIS (MVIS) = set of all horizontal (vertical) DPs The dicing plan which slices out dice 1 and

Interval Coloring Two dice are in H-conflict iff their vertical projections overlap  Interval graph, which can be optimally colored All dice of the same color can be horizontally sliced out

Non-Linear Programming Formulation Assume the wafer is a rectangular array of prints. f H = # rows (with DP H) one DP per row = # rows whose dicing plans slice out D i

Non-Linear Programming Formulation Assume the wafer is a rectangular array of prints. g V = # columns (with DP V) = # columns whose dicing plans slice out D i one DP per column

Non-Linear Programming Formulation N(D i )= # required copies of die D i z=1/(# wafer) copies sliced out Must slice out at least the required volume

Non-Linear Programming Formulation Assume the wafer is a rectangular array of prints. f H = # rows (with DP H) g V = # columns (with DP V) N(D i )= # required copies of die D i Maximize: z = 1/(# wafers) Subject to:

Integer Linear Programming Formulation One DP per row

Integer Linear Programming Formulation One DP per column

Integer Linear Programming Formulation The print at r th row and c th column is diced by DP H and V iff we use H at the r th row and V at the c th column

Integer Linear Programming Formulation D i sliced out otherwise Sliced out at least required volume

Integer Linear Programming Formulation Maximize: z = 1/(# wafers) Subject to:

Iterative Augment and Search Algorithm (IASA) Choose initial dicing plan using interval graph coloring DP 1 DP 2

Iterative Augment and Search Algorithm (IASA) Choose initial dicing plan using interval graph coloring In each iteration, first check whether z will increase by changing the dicing plan for one row or column DP 1,…,DP |MVIS| DP 1 DP 2 DP 1,…,DP |MHIS|

Iterative Augment and Search Algorithm (IASA) Choose initial dicing plan using interval graph coloring In each iteration, first check whether z will increase by changing the dicing plan for one row or column DP 1 DP 2 DP 1,…,DP |MHIS| Choose one dicing plan for one new row or column which maximizes z DP 3

Experiment Setup Ten random testcases with different numbers of dice Required production volume is 40 for all dice Assume a wafer has 10 rows and 10 columns of prints We used CPLEX to solve LP We used LINGO 6.0 to solve NLP We implemented the IASA heuristic in C All tests are run on an Intel Xeon 2.4GHz CPU

Experimental Results for SSDP Test Case # dice NLP-LingoLP-CPLEXIASA 40zCPU(s)40zCPU(s)40zCPU(s) Performance of IASA is much better

Introduction to Multi-Project Wafer Outline Side-to-side wafer dicing problem Reticle floorplanning and wafer dicing problem Conclusions and future research directions Experimental results Design flow

What Floorplan is Good? 40 wafers needed for 40 copies Min-area floorplan  high wafer cost

What Floorplan is Good? 40 wafers needed for 40 copies Min-area floorplan  High wafer cost Diagonal floorplan  Larger reticle  High wafer cost

What Floorplan is Good? 40 wafers needed for 40 copies Min-area floorplan  high wafer cost Diagonal floorplan  high mask cost wafers needed for 40 copies Good floorplan

Reticle Design and Wafer Dicing Problem Given: n dice D i (i=1…n), reticle size Find: placement of dice within the reticle and a dicing plan To Minimize: w, the number of wafers used

Shelf Packing and Shifting Sort dice according to height

Shelf Packing and Shifting Sort dice according to height For all possible shelf widths, insert the dice into the shelves

Shelf Packing and Shifting Sort dice according to height For all possible shelf widths, insert the dice into the shelves Shift the dice to align them with the dice on other shelves and calculate z using IASA

Shelf Packing and Shifting Choose the placement with the max z Sort dice according to height For all possible shelf widths, insert the dice into the shelves Shift the dice to align them with the dice on other shelves and calculate z using IASA

Simulated Annealing Placement Get a shelf packing floorplan as the initial floorplan Calculate Objective Value =(1-α) area+ α(100-z) While (not converge and # of move < Move_Limit) { choose a uniform random number r make a random move according to r calculate δ = New Objective Value - Old Objective value If (δ <0) Accept the move Else Accept the move with probability exp(- (δ/T)) T=β T }

Introduction to Multi-Project Wafer Outline Side-to-side wafer dicing problem Reticle floorplanning and wafer dicing problem Conclusions and future research directions Experimental results Design flow

Experimental Results for RDWDP Test Case # Die Die area GTMuchShelf+shiftSA+IASA 40zarea40zareaCPU40zareaCPU Total GTMuch is a commercial tool for MPW Improve wafer yield z by 37.7% compared with GTMuch Improve wafer yield z by 30.5% compared with shelf+shift

Solutions for Testcase 1 GTMuch Parquet Simulated annealingShelf+shift

Introduction to Multi-Project Wafer Outline Side-to-side wafer dicing problem Reticle floorplanning and wafer dicing problem Conclusions and future research directions Experimental results Design flow

Conclusions We presented a MPW design flow We propose practical mathematical programming formulations and efficient heuristics, which can be extended to the case when margins are allowed By using the simulated annealing code, we can further improve wafer-dicing yield by 30.5% at the expense of an increase of area by 3.3%. The shelf packing and shifting algorithm can improve yield by 37.7% while reducing reticle area by 3.3% compared to GTMuch.

Future Research Validate proposed methods on industry testcases Extend the proposed algorithms to round wafer Multiple dicing plans

Thank you for your attention!