Stack Memory 00000 H 00001 H FFFFF H FFFFE H SS 0105 SP 0008 TOS BOS BOS = 01050+FFFF = 1104F H 01058 H 1104F H.

Slides:



Advertisements
Similar presentations
Stack Memory 00000H 00001H 01058H TOS SS SP 1104FH BOS
Advertisements

Register In computer architecture, a processor register is a small amount of storage available on the CPU whose contents can be accessed more quickly than.
Chapter 2 (cont.) An Introduction to the 80x86 Microprocessor Family Objectives: The different addressing modes and instruction types available The usefulness.
COMP 2003: Assembly Language and Digital Logic
MICROPROCESSORS TWO TYPES OF MODELS ARE USED :  PROGRAMMER’S MODEL :- THIS MODEL SHOWS FEATURES, SUCH AS INTERNAL REGISTERS, ADDRESS,DATA & CONTROL BUSES.
Computers organization & Assembly Language
CEN 226: Computer Organization & Assembly Language :CSC 225 (Lec#3) By Dr. Syed Noman.
Chapter 3 Addressing Modes
Chapter Four–80x86 Instruction Set Principles of Microcomputers 2015年5月17日 2015年5月17日 2015年5月17日 2015年5月17日 2015年5月17日 2015年5月17日 1 Chapter four 80x86.
6-1 ECE 424 Design of Microprocessor-Based Systems Haibo Wang ECE Department Southern Illinois University Carbondale, IL Intel 8088 Addressing modes.
Lect 3: Instruction Set and Addressing Modes. 386 Instruction Set (3.4) –Basic Instruction Set : 8086/8088 instruction set –Extended Instruction Set :
Azir ALIU 1 What is an assembly language?. Azir ALIU 2 Inside the CPU.
Handout 2 Digital System Engineering (EE-390)
Data Movement Instructions
Addressing modes – 1 The way in which an operand is specified is called the Address Mode.
The 8086 Assembly Programming Data Allocation & Addressing Modes
Addressing Modes Instruction – Op-code – Operand Addressing mode indicates a way of locating data or operands. – Any instruction may belong to one or more.
3-1 ECE 424 Design of Microprocessor-Based Systems Haibo Wang ECE Department Southern Illinois University Carbondale, IL Intel 8088 (8086) Microprocessor.
Microprocessor Systems Design I Instructor: Dr. Michael Geiger Spring 2013 Lecture 4: 80386DX memory, addressing.
Lect 4: Instruction Set and Addressing Modes. 386 Instruction Set (3.4)  Basic Instruction Set : 8086/8088 instruction set  Extended Instruction Set.
An Introduction to 8086 Microprocessor.
1/2002JNM1 Positional Notation (Hex Digits). 1/2002JNM2 Problem The 8086 has a 20-bit address bus. Therefore, it can access 1,048,576 bytes of memory.
Types of Registers (8086 Microprocessor Based)
INSTRUCTION SET AND ASSEMBLY LANGUAGE PROGRAMMING
ECE291 Computer Engineering II Lecture 3 Josh Potts University of Illinois at Urbana- Champaign.
UHD:CS2401: A. Berrached1 The Intel x86 Hardware Organization.
Microprocessor Microprocessor (cont..) It is a 16 bit μp has a 20 bit address bus can access upto 220 memory locations ( 1 MB). It can support.
ΠΟΛΥΤΕΧΝΙΚΗ ΣΧΟΛΗ Τμήμα Ηλεκτρολογών Μηχανικών και Τεχνολογίας Υπολογιστών Μικρουπολογιστές & Μικροσυστήματα ΙΙ Καθηγητής Σταύρος Α. Κουμπιάς Πανεπιστημίου.
ECE291 Computer Engineering II Lecture 3 Josh Potts University of Illinois at Urbana- Champaign.
ECE291 Computer Engineering II Lecture 3 Dr. Zbigniew Kalbarczyk University of Illinois at Urbana- Champaign.
Intel 8086 (8088) Microprocessor Structure
University of Tehran 1 Microprocessor System Design Omid Fatemi Machine Language Programming
Assembly Language Data Movement Instructions. MOV Instruction Move source operand to destination mov destination, source The source and destination are.
Internal Programming Architecture or Model
1 x86 Programming Model Microprocessor Computer Architectures Lab Components of any Computer System Control – logic that controls fetching/execution of.
Microprocessors CSE- 341 Dr. Jia Uddin Assistant Professor, CSE, BRAC University Dr. Jia Uddin, CSE, BRAC University.
Intel MP Organization. Registers - storage locations found inside the processor for temporary storage of data 1- Data Registers (16-bit) AX, BX, CX, DX.
SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSORS
I NTEL 8086 M icroprocessor بسم الله الرحمن الرحيم 1.
Addressing Modes Instruction – Op-code – Operand Addressing mode indicates a way of locating data or operands. – Any instruction may belong to one or more.
Microprocessors CSE- 341 Dr. Jia Uddin Assistant Professor, CSE, BRAC University Dr. Jia Uddin, CSE, BRAC University.
Computer Science 516 Intel x86 Overview. Intel x86 Family Eight-bit 8080, 8085 – 1970s 16-bit 8086 – was internally 16 bits, externally 8 bits.
ΜComputer Structure μProcessor Memory Bus System I/O Ports.
Instruction set Architecture
Microprocessor Systems Design I
Introduction to 8086 Microprocessor
COURSE OUTCOMES OF MICROPROCESSOR AND PROGRAMMING
16.317: Microprocessor System Design I
ADDRESSING MODES.
Assembly IA-32.
ADDRESSING MODES.
University of Gujrat Department of Computer Science
Intel 8088 (8086) Microprocessor Structure
Chapter 3 Addressing Modes
Symbolic Instruction and Addressing
Introduction to Assembly Language
Data Addressing Modes • MOV AX,BX; This instruction transfers the word contents of the source-register(BX) into the destination register(AX). • The source.
Intel 8088 (8086) Microprocessor Structure
8086 Registers Module M14.2 Sections 9.2, 10.1.
CS-401 Computer Architecture & Assembly Language Programming
Morgan Kaufmann Publishers Computer Organization and Assembly Language
32-bit instruction mode(80386-Pentium 4 only)
Symbolic Instruction and Addressing
Symbolic Instruction and Addressing
CNET 315 Microprocessor & Assembly Language
Lecture 06 Programming language.
Computer Architecture CST 250
Unit-I 80386DX Architecture
Chapter 6 –Symbolic Instruction and Addressing
Intel 8086.
Presentation transcript:

Stack Memory H H FFFFF H FFFFE H SS 0105 SP 0008 TOS BOS BOS = FFFF = 1104F H H 1104F H

PUSH AX TOS 1234 H AX 1058 H XX H 1057 H 1056 H 1055 H Before execution 1058 H XX H 34 H 12 H XX H 1057 H 1056 H 1055 H TOS After execution

POP BX 1234 H BX Before execution 1058 H XX H 34 H 12 H XX H 1057 H 1056 H 1055 H TOS After execution 1058 H XX H 34 H 12 H XX H 1057 H 1056 H 1055 H XXXX H BX TOS

I/O address space open reserved 00F8 H 00FF H 0000 H FFFF H A separate 64 Kbyte address space is provided where I/O interfaces are implemented. Certain I/O instructions can only perform operations to I/O devices located in this I/O address space.

Addressing modes of the 8086 / 8088 μP Register addressing mode MOV AX, BX MOV destination operand, source operand XXXX H AX 1234 H BX Before the execution 1234 H AX 1234 H BX After the execution

Coding in machine language opcode D W Operation code D= 1 direction is to the register specified in byte 2 D=0 direction is from the register specified in byte 2 Byte 1Byte 2 mod reg R/M W=0 8 bit data w=1 16 bit data 00 memory mode no displacement 01 Memory mode, 8 bit displacement 10 Memory mode 16 bit displacement 11 Register mode no displacement mod Except when R/M =110, 16 bit displacement follows

MOD = 11Effective address ( offset ) calculation 000 AL AX000 [BX]+[SI] [BX]+[SI]+D8 [BX]+[SI]+D CL CX001 [BX]+[DI] [BX]+[DI]+D8 [BX]+[DI]+D DL DX010 [BP]+[SI] [BP]+[SI]+D8 [BP]+[SI]+D BL BX011 [BP]+[DI] [BP]+[DI]+D8 [BP]+[DI]+D AH SP100 [SI] [SI]+D8 [SI]+D CH BP101 [DI] [DI]+D8 [DI]+D DH SI110 Direct address [BP]+D8 [BP]+D BH DI111 [BX] [BX]+D8 [BX]+D16 R/M W=0 W=1 R/M MOD=00 MOD=01 MOD=10

General Instruction Format Byte 1Byte 2Byte 3Byte 4Byte 5Byte 6

MOV BL,AL Register / memory to/ from register dw Mod reg r/m Displ-lo Displ-hi Machine code c3 H Assembly code

Immediate addressing mode MOV AL, 15H MOV destination operand, immediate source operand XXXX H AX Before the execution XXA5 H AX After the execution Immediate operand must begin with 0-9 MOV AL, 0A5H

Immediate to register 1011 w reg data Data if w=1 MOV AL, 15H Assembly codeMachine code B015 H

Direct addressing mode The memory locations following the instruction op code hold an effective memory address MOV AX, [0004] Register / memory to / from register dwMod reg r/mDisp-loDisp-hi b The logical address is [DS] : [ 0004]

μPμP 0000 IP XXXX CS DS SS ES AX μPμP 0004 IP BEED CS DS SS ES AX 8B ED BE 8B ED BE XX MOV AX, [0004] Before executionAfter execution Direct addressing mode

Register indirect addressing mode MOV AX, [SI] The logical address is [DS] : [BX] or [DS] : [SI] or [DS] : [DI] μPμP 0000 IP XXXX CS DS SI AX 8B 04 XX ED BE μPμP 0002 IP BEED CS DS SI AX 8B 04 XX ED BE

MOV AX, [SI] Register / memory to/ from register dw Mod reg r/m Displ-lo Displ-hi Machine code B04 H Assembly code

Indexed addressing mode Logical address = [ DS] : [SI] + direct or indirect displacement [DS] : [DI] + direct or indirect displacement or MOV AL,[SI]+1234H Register / memory to / from register dwMod reg r/mDisp-loDisp-hi A843412

Based addressing mode Logical address = [ DS] : [BX] + direct or indirect displacement [SS] : [BP] + direct or indirect displacement or MOV [BX]+1234H,AL Register / memory to / from register dwMod reg r/mDisp-loDisp-hi

Based addressing mode MOV [BX]+1234 H, AL μPμP 0000 IP BEED CS DS SI AX XX μPμP 0004 IP BEED CS DS SI AX 8B 04 XX ED XX BX

Indexed addressing mode MOV AL,[SI]+1234H μPμP 0000 IP XXXX CS DS SI AX 8A BE μPμP 0004 IP XXBE CS DS SI AX 8A BE