Roadmap for Carbon Nanotubes and Graphene ITRS Logic Workshop Tsukuba, Japan George Bourianoff facilitating Sept 23, 2008

Workshop and Business Meeting Objectives (Sept. 22 – 23) Layout roadmap for Carbon Nanotubes and Graphene for “Ultimately Scaled CMOS” and “Beyond CMOS”. Build on results from July ERD meetings. – Ultimate CMOS roadmap – potential solution (PIDS Role?) – Beyond CMOS roadmap entry – current ERD format? Provide information needed to develop new Memory Table entries for STT RAM (new TE for 2009). Determine content for 2009 ERD logic section – Review Technology Entries (TEs) from 2007 – Review potential TE adds/drops for 2009 – Solicit writing volunteers for 2009 Discuss linkage to materials and architecture sections – How can we improve the integration? (e.g. joint workshops, key materials properties table, …) Approximate timeline for 2009 ERD Business meeting

Agenda Review objectives, desired outcome and timeline of roadmapping exercise Present and discuss strawman structure based on ITRS “potential solution format” Discuss table contents (Technology Entries) Discuss next steps

Objectives Identify infrastructure requirements and gaps to fabricate industrially relevant, carbon based prototype devices with timeline Identify key infrastructure requirements neede to develop new functionalities of carbon based electronics with timeline

Work in Progress --- Not for Publication 5 ERD WG 9/22-23/08 Scope of roadmap discussion Integrate with other known technology roadmaps to achieve commercial viability Identify critical infrastructure requirements to fabricate industrially relevant prototypes Identify existing infrastructure & infrastructure gaps Decide roadmap format – e.g. potential solution format – Decide major technology entries – Determine approximate timelines

Work in Progress --- Not for Publication 6 ERD WG 9/22/08 Carbon-based Nanoelectronics Workshop Agenda 9:30 Introduction Dr. Y. Awano (Fujitsu) 9:40 “Theory of electronic states and Prof. T. Ando (Tokyo Inst. Tech) transport in graphene and nanotube” 10:30 “Graphene conduction control by gate Dr. K. Tsukagoshi (AIST) voltage 11:20 “Epitaxial graphene on Si substrate Prof. M. Suemitsu (Tohoku U.) mediated by an ultra-thin SiC layer” 12:10 Lunch 13:00 “Evaluation of number of graphene Dr. H. Hibino (NTT) layers grown on SiC” 13:50 “Beyond-CMOS applications of Prof. P. Kim (Columbia U.) graphene based nanoelectronics” 14:40 Summary Dr. Y. Awano (Fujitsu) 15:00 Spin Torque Transfer RAM Workshop Dr. U-In Chung (Samsung)

Proposed roadmap format Build on ITRS “potential solution” format Separate into FET driven requirements and novel device infrastructure requirements Tie closely and directly to ERM

ERM table of applications vs TWIG Insert new column here??

Proposed structure - table 1

Proposed structure –table 2

Discussion on table structure Recognizes need for improved samples regardless of specific applications Recognizes that some applications will drive special needs e.g. FETs Will this structure accomplish our objective? Is there a better structure

Table contents General Requirements Device Specific Requirements

Timeline Circulate proposal to entire group Merge all inputs in December Solicit volunteers for specific topics Schedule regular meetings in spring Output in time for spring meeting

Content of 2009 ERD Logic section ITRS Logic Workshop Tsukuba, Japan George Bourianoff facilitating Sept

Work in Progress --- Not for Publication 15 ERD WG 9/22-23/08 Workshop and Business Meeting Objectives (Sept. 22 – 23) Layout roadmap for Carbon Nanotubes and Graphene for “Ultimately Scaled CMOS” and “Beyond CMOS”. Build on results from July ERD meetings. – Ultimate CMOS roadmap – potential solution (PIDS Role?) – Beyond CMOS roadmap entry – current ERD format? Provide information needed to develop new Memory Table entries for STT RAM (new TE for 2009). Determine content for 2009 ERD logic section – Review Technology Entries (TEs) from 2007 – Review potential TE adds/drops for 2009 – Solicit writing volunteers for 2009 Discuss linkage to materials and architecture sections – How can we improve the integration? (e.g. joint workshops, key materials properties table, …) Approximate timeline for 2009 ERD Business meeting

Objectives Determine content for 2009 ERD logic section Review Technology Entries (TEs) from 2007 Review potential TE adds/drops for 2009 Solicit writing volunteers for 2009 Discuss linkage to materials and architecture sections How can we improve the integration? (e.g. joint workshops, key materials properties table, …) Approximate timeline for 2009 ERD Business meeting

High performance logic table 2007

2007 Technology Entries – High Performance Extensions to CMOS - Low dimensional structures previously included Carbon Nanotube FETs, nanowire FETs, and Nanowire heterostructures. This edition will also include nanoribbon devices using graphene.. 2. Extensions to CMOS - High mobility channel replacement FETs including III-V and Ge channel replacement 3. Single electron devices discussion had similar scope to previous editions 4. Molecular devices had similar scope to previous editions with primary focus on molecule on CMOS architecture (CMOL) concept 5. Ferromagnetic logic devices are based on collective magnetic effects associated with the magnetic polarity of a nanodomain. 6. Spin devices are based on spin dynamics of one or a few electrons, defects, or nuclei

2007 Alternative Device Table

2007 Technology Entries Alternative Information Processing 1. Resonant Tunneling Diodes 2. Multi-ferroic Tunnel Junctions 3. Single Electron Transistors 4. Molecular Devices 5. Ferro-Magnetic Devices 6. Frequency Coherent Spin Devices

Suggestions received Include a discussion of hybrid devices –Not sure that makes sense at the device level –Proposal – make the point in the intro that some applications may benefit from a hybrid approach Include steep subthreshold devices –They are in the transition table –Should we keep them there? Include MQCA as a category –It already is in the alternative device table – no action needed Nanocrystal flash devices for logic –It already is in the alternative device table – no action needed

2007 Transition table

New topics for discussion –Should we broaden the “high performance” table to include Low Power” and “Low Standby Power”? (Call it “High Volume” applications?) –Pros Would align better with ITRS System Drivers Would reflect motivation of much research Several recent theoretical and simulation papers support this –Con Would be orthogonal to the historical “tracking” function of the Table

Technology Entries(1) FET extensions –Low dimension Channel replacement category Recommend keeping category perhaps emphasizing carbon based components Discuss CNTFETs with PIDs –High mobility channel replacements Send III-V and Ge to PIDs Graphene keep or talk to PIDs

SETs Recommend keeping but emphasize low power application –Pros A lot of recent work supports that. (Very recent paper by Vishwa Ray at UT Arlington* shows RT operation self aligned process on Si) –Cons Past efforts have not been fruitful Stray charge will always be problem Nature of Nanotechnology advance online

Molecular Recommend moving to transition table and keeping in the alternate technology table Pros –Recent progress has been weak Cons –Many people believe passionately that it still has great potential

Ferromagnetic and spin transistor Recommend keeping categories but merging them together Pros –Line between the two entries is becoming blurred as we heard yesterday –Large amount of activity in area (driven currently by memory including embedded) Cons –??

New Technology Entries to consider ???

2007 Technology Entries Alternative Information Processing 1. Resonant Tunneling Diodes 2. Multi-ferroic Tunnel Junctions 3. Single Electron Transistors 4. Molecular Devices 5. Ferro-Magnetic Devices 6. Frequency Coherent Spin Devices

Resonant Tunnel Diodes Recommend moving to transition table Pros –Not much progress Cons –It is an interesting device with NDR –Many people feel passionately about it

Multiferroic tunnel junctions Recommendation – change the category to multiferroic switching elements Pros –Recent demonstration of RT mutiferroic properties in BFO –Several applications in low power spin wave circuits –Main application would be 4 state logic which is not attractive for other reasons Cons –???

Single Electron Transistors Recommendation- Keep category as it is Pros –Potential Non Boolean logic applications such as image recognition still receiving attention –Still an active area Cons –???

Molecular devices Recommendation – Keep the category Pros –Area of intense activity –Driven by nano bio –New applications being constantly proposed Cons –????

Ferromagnetic devices Recommendation – Keep the category –Pros Area of intense activity Potential applications and devices outside of Boolean Logic gates Include Graphene devices –Cons ????

Coherent spin devices Recommendation – Keep the category –Pros Significant activity taking place Pseuduospintronic devices on bilayer graphene would go here Spin hall effect devices would go here (also on graphene most likely) –Cons Single spins at room temperature will never be robust (?) and therfore should drop