1 Registers and MAL - Part I. Motivation So far there are some details that we have ignored instructions can have different formats most computers have.

Slides:



Advertisements
Similar presentations
Instruction Set Design
Advertisements

Goal: Write Programs in Assembly
INSTRUCTION SET ARCHITECTURES
There are two types of addressing schemes:
ELEN 468 Advanced Logic Design
ITCS 3181 Logic and Computer Systems 2015 B. Wilkinson slides3.ppt Modification date: March 16, Addressing Modes The methods used in machine instructions.
Computer Organization and Architecture
Computer Organization and Architecture
Computer Organization and Architecture
LC-3 Computer LC-3 Instructions
Execution of an instruction
CSCE 121, Sec 200, 507, 508 Fall 2010 Prof. Jennifer L. Welch.
CH11 Instruction Sets: Addressing Modes and Formats
Implementation of a Stored Program Computer
Chapters 1 and 8 Abstractions and Computers and the MAL programming Language.
Part II: Addressing Modes
Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz.
CH12 CPU Structure and Function
Processor Organization and Architecture Module III.
4-1 Chapter 4 - The Instruction Set Architecture Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring.
Instruction Set Architecture
COMP2011 Assembly Language Programming and Introduction to WRAMP.
Instruction Set Architecture
Memory and Addressing How and Where Information is Stored.
December 8, 2003Other ISA's1 Other ISAs Next, we discuss some alternative instruction set designs. – Different ways of specifying memory addresses – Different.
Chapter 5 A Closer Look at Instruction Set Architectures.
Chapter 2-2 Assembly Instructions Number Systems Number Systems Assembly Instructions Assembly Instructions Branch Branch Next Lecture Next Lecture  Addressing.
Module 3 Instruction Set Architecture (ISA): ISA Level Elements of Instructions Instructions Types Number of Addresses Registers Types of Operands.
4-1 Chapter 4 - The Instruction Set Architecture Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Principles.
Execution of an instruction
Module : Algorithmic state machines. Machine language Machine language is built up from discrete statements or instructions. On the processing architecture,
COMPUTER ARCHITECURE INSTRUCTION SET ARCHITECTURE.
Computer Organization
Represents different voltage levels High: 5 Volts Low: 0 Volts At this raw level a digital computer is instructed to carry out instructions.
ECEG-3202 Computer Architecture and Organization Chapter 6 Instruction Sets: Addressing Modes and Formats.
Instruction Sets: Addressing modes and Formats Group #4  Eloy Reyes  Rafael Arevalo  Julio Hernandez  Humood Aljassar Computer Design EEL 4709c Prof:
COMPUTER ORGANIZATION AND ASSEMBLY LANGUAGE Lecture 21 & 22 Processor Organization Register Organization Course Instructor: Engr. Aisha Danish.
Addressing Modes and Formats
What is a program? A sequence of steps
Arrays in MIPS Assembly Computer Organization and Assembly Language: Module 6.
Lecture 2: Instruction Set Architecture part 1 (Introduction) Mehran Rezaei.
Computer Organization Instructions Language of The Computer (MIPS) 2.
F453 Module 8: Low Level Languages 8.1: Use of Computer Architecture.
Computer Architecture
Displacement (Indexed) Stack
William Stallings Computer Organization and Architecture 6th Edition
Immediate Addressing Mode
Alvaro Mauricio Peña Dariusz Niworowski Frank Rodriguez
William Stallings Computer Organization and Architecture 8th Edition
Processor Organization and Architecture
BIC 10503: COMPUTER ARCHITECTURE
Computer Organization and ASSEMBLY LANGUAGE
The University of Adelaide, School of Computer Science
ECEG-3202 Computer Architecture and Organization
Introduction to Micro Controllers & Embedded System Design
Computer Architecture
Classification of instructions
CPU Structure and Function
William Stallings Computer Organization and Architecture 8 th Edition Chapter 11 Instruction Sets: Addressing Modes and Formats.
Presentation transcript:

1 Registers and MAL - Part I

Motivation So far there are some details that we have ignored instructions can have different formats most computers have more than one kind of memory a real assembly language has no notion of data type

Instructions as Data A program code can be thought of as an array of instructions Many modern computers, including MIPS RISC architecture, have fixed-sized instructions that are at least 32-bits long. The advantage of fixed-size instructions is the ease of calculating where it begins and ends, especially if the size is equal to a word.

Large instructions not only take up space but require more time to fetch, thus there is an advantage to small instructions. add a bc opcode

Opcode The opcode corresponds to the mnemonic of an assembly language instruction -- e.g. it tells us that it is an add instruction. Implicitly, it specifies how the other fields have to be interpreted. The opcode must be specified by a field large enough to specify uniquely all possible codes in the instruction set.

How many bits do we need for the add instruction? = 104 bits Each memory access can only take 32 bits at a time. Fetch instruction = 4 accesses Fetch and store operands = 3 accesses

Reducing the size of an instruction reduces the size of the program in memory. It also reduces the time and amount of hardware needed to fetch the instruction. The motivation for techniques to reduce instruction size is based on locality of reference property.

Locality of Reference A small and predictable set of variables tends to be referenced much more often than other variables. This property implies that the memory is not referenced randomly. This property is also used to enhance speed using a cache.

Three-address format A SAL instruction add a,b,c requires three things to be specified: The two numbers to be added and the destination to which the result of the addition is to be saved. This instruction format is called a three- address format.

Two-address format The address of an instruction can often be inferred from its context. If we use only one specification for both the destination of the operation result and one of the operands, then we make the instruction shorter. add a,b # a = a + b

One-address format We can reduce the size of the instruction further by using an accumulator. An accumulator is a special memory cell used as the destination for most instruction results. add a #accumulator=accumulator + a

Example 11.1 The high-level language statement a = b + c; can be translated as: accumulator = b accumulator = accumulator + c a = accumulator

Store and Load Instructions To assign the value of the variable x to the accumulator we can use the instruction lda x To store the value of the accumulator to x we can use the instruction sta x

Example 11.2 We can translate the high-level language statement a = b + c; using the load and store instructions into: lda b add c sta a

Example 11.3 The use of single-address instructions need not dramatically increase the number of instructions as we might expect. avg = (a + b + c + d)/ 4; add avg,a,b add avg,avg,c add avg,avg,d div avg,avg,4 lda a add b add c add d div 4 sta avg SAL three-address format one-address format high-level

Registers In practice, registers are designed to be a part of the CPU and not a part of memory. Register set or register files can be considered as a second, small memory. Since this is a small memory, the number of addresses become small and thus, the number of bits required to store the addresses reduce. An individual word within this small memory is called a register.

The variables that are used more often are assigned more or less permanently to individual registers. Other variables that are not used often can be temporarily assigned to any unused register. The values of the variables must be copied to the register when the register is bound to the variable and are copied back into memory when the registers are unbound. Hence, many variables can share the same register in the course of the program.

The MIPS RISC architecture get their operands only from the registers. The only instructions that are allowed to access the memory are the load and store instructions. Architectures that restrict the access of data in memory to load and store instructions are called load and store architectures. A register is specified by preceding its name by the symbol $. sub $10, $8, $9

Special Registers Some registers are special purpose registers like the PC (program counter) or may be use to hold frequently used memory address like the stack pointer. In MIPS RISC architecture, $0 always contains the constant 0.

Addressing Modes The effective address is the address after all the calculations are completed. Addressing mode is the method by which an address is specified 1. Direct. Use a two-word instruction. The address is contained in the instruction. address opcodereg effective address

2. Register Direct. Specify a register that contains the effective address opcodereg address effective address

3. Base Displacement/Indexed/Relative. Specify a register and a constant. The address is computed by adding them together. opcoderegconstant address + effective address

The instruction specifies two registers containing two addresses. The sum is the effective address. opcode reg addressoffset effective address +

Immediate. The operand is contained directly in the instruction. Register. The operand is contained in a register. Indirect. The instruction specifies a register which contains a first address. The first address does not contain the operand but contains a second address where the operand is located.

Indirect Addressing address opcodereg address effective address

Control Instructions In a load/store architecture, only two types of instructions specify addresses: store and load instructions control instructions Control instructions specify the target address of the next instruction if the control of the program execution is to be transferred there, e.g. branch, jump

PC-relative addressing A machine language instruction can specify an offset to a jump. The offset is added to the value of the PC to find the effective address of the next instruction. An addressing mode that implies the use of a PC is PC-relative. offset beqvar1var2 program counter (PC) address + effective address