High-Level Constructors and Estimators Majid Sarrafzadeh and Jason Cong Computer Science Department

An Overview of PACT Architectural Primitives Cells Application in C PACT cc PACT sim PACT Estimate PACT Synth Commodity System Application Specific System

Overview of PACT Power Aware Compilers 1. Optimization framework 2. Library function characterizations 3. High-level transformations 4. Low-level transformations Power Aware CAD 1. Behavioral power estimation 2. Behavioral low-power synthesis 3. Logic level power estimation 4. Logic level low-power synthesis Power-Aware Applications 1.Enable new missions 2.Enable new capabilities Power Aware Architectures 1. Develop power aware methodologies 4. Software/hardware techniques 2. Apply methods to specific structures 5. Profiling techniques 3. Hardware only techniques

Power Aware CAD Behavioral level high-level power estimation Behavioral level high-level power estimation  Estimate power consumption at RTL VHDL level using switching tables Behavioral level low-power synthesis Behavioral level low-power synthesis  Use high-level power estimation to drive CDFG operation scheduling and resource allocation for low-power Logic/layout level accurate power estimation Logic/layout level accurate power estimation  Develop stochastic techniques for combinational and sequential circuits Logic/layout level low-power synthesis Logic/layout level low-power synthesis  Use power estimators to perform low-power logic synthesis such as gate sizing, clock gating

Power Aware CAD RTL VHDL Input Parser Builds CDFG Behavioral power estimator Behavioral synthesis (Schedule, Allocate, floorplan) Logic power estimate (deterministic, prob. stochastic) Logic synthesis (global factoring local resizing) Netlist of gates with power control Power models Resource library Resource characterize Compiler Architecture

High Level Power Estimation: Motivation The breed of new systems is going to be ultra complex with rich computational functionality and networking capabilities. The breed of new systems is going to be ultra complex with rich computational functionality and networking capabilities. These devices will be mobile and low power will be a major concern in their design process. These devices will be mobile and low power will be a major concern in their design process. Efficient power estimation technique will enable faster time to market. Efficient power estimation technique will enable faster time to market.

Power Estimation: Requirements Quick estimation methodology to enable efficient design space exploration Quick estimation methodology to enable efficient design space exploration The estimation methodology should be sufficiently “early on” to enable large improvements The estimation methodology should be sufficiently “early on” to enable large improvements It should strike the correct balance between simplicity in abstraction and accuracy of prediction It should strike the correct balance between simplicity in abstraction and accuracy of prediction It should not go through the whole flow of Logic Synthesis and Physical Design to do the estimation It should not go through the whole flow of Logic Synthesis and Physical Design to do the estimation

Our Approach Study of the Effects of Individual optimization steps in the design process on the overall accuracy of power prediction. Study of the Effects of Individual optimization steps in the design process on the overall accuracy of power prediction. This would enable us come up with confidence numbers associated with each prediction. These confidence numbers could be used by optimization steps to drive architectural exploration This would enable us come up with confidence numbers associated with each prediction. These confidence numbers could be used by optimization steps to drive architectural exploration

Points FACT: Certain designs are more predictable than others, example simple DFG kind of computations can have higher predictability than designs with loops and conditional statements FACT: Certain designs are more predictable than others, example simple DFG kind of computations can have higher predictability than designs with loops and conditional statements Question: WHY? To answer this we will study the effects of various computations of accuracy. To answer this we will study the effects of various computations of accuracy.

Some Preliminary Results + C2C1C0C3 FIR Filter

Scheduling and Binding Solution-I * * * * Binding Of Operations Clock-1 Clock-2 Clock-3 Clock-4 Two Adders, Two Multipliers

Scheduling and Binding Solution-II * * * * Binding Of Operations Clock-1 Clock-2 Clock-3 Clock-4 Two Adders, Two Multipliers

Comparison For Solution I  Combinational Gate Area: 815  Flip Flop Area: 631  Power: 3.20 uw For Solution II  Combinational Gate Area: 823  Flip Flop Area: 687  Power: 3.20 uw Solution X (changing resources): all over the map

Framework Of Expriments Synopsys BC, DC and Power Compiler Synopsys BC, DC and Power Compiler The Power values were obtained by doing an RTL simulation of the design and extracting the switching activity. This activity was annotated to the gate level netlist and power values were extracted at gate level The Power values were obtained by doing an RTL simulation of the design and extracting the switching activity. This activity was annotated to the gate level netlist and power values were extracted at gate level

Basic Analysis of Results If the number of clock cycles and number of resources do not change, If the test vectors are randomly distributed, then there is not a significant variation in the power value of various bindings for DFG kind of applications. Hence estimation at this step should have a high value of predictability. If the number of clock cycles and number of resources do not change, If the test vectors are randomly distributed, then there is not a significant variation in the power value of various bindings for DFG kind of applications. Hence estimation at this step should have a high value of predictability. This claim has to be validated by a lot of experimentation with much larger benchmarks This claim has to be validated by a lot of experimentation with much larger benchmarks

Needs for Efficient Interconnect Estimation Models Efficiency Efficiency Abstraction to hide detailed design information Abstraction to hide detailed design information  granularity of wire segmentation  number of wire widths, buffer sizes,... Explicit relation to enable optimal design decision at high levels Explicit relation to enable optimal design decision at high levels Ease of interaction with logic/high level synthesis tools Ease of interaction with logic/high level synthesis tools

Develop a set of interconnect performance estimation models (IPEM), under different optimization alternatives: Develop a set of interconnect performance estimation models (IPEM), under different optimization alternatives:  Optimal Wire Sizing (OWS)  Simultaneous Driver and Wire Sizing (SDWS)  Simultaneous Buffer Insertion and Wire Sizing (BIWS)  Simultaneous Buffer Insertion/Sizing and Wire Sizing (BISWS) Interconnect Performance Estimation Modeling [Cong-Pan, ASPDAC’99, TAU’99, DAC’99]

Area Estimation for OWS

Some Applications of IPEM Layout-driven physical and RTL level floorplanning Layout-driven physical and RTL level floorplanning  Predict accurate interconnect delay and routing resource without really going into layout details;  Use accurate interconnect delay/area to guide floorplanning/placement Interconnect Architecture Planning Interconnect Architecture Planning  E.g. Wire width planning Floorplanning + interconnect planning Floorplanning + interconnect planning  E.g. Buffer block planning Available from Available from

Conclusions Prediction can be done only on some specific problems Prediction can be done only on some specific problems  Classify problems/steps that are predictable To get good estimation, we may have to construct/commit To get good estimation, we may have to construct/commit  More so, as more degrees of freedom (clock gating, sleep more, architectural “tricks”, …) How to effectively combine predictors and constructors? How to effectively combine predictors and constructors? {majid,