abk C.A.D. Intellectual Agenda u Roadmapping: “Living Roadmap” to connect applications, architectures, components, technologies s Design envelopes; Impacts of innovations; FCRP portfolio gaps s Synergies: Drivers, Power-Energy, Reliability, C2S2 Fabrics, MSD, IFC u Focus on SiP physical implementation platforms (CLC, SOS) s Huge hole in FCRP understanding s Need technology and cost modeling, tools, implementation, roadmapping s Concrete high-end design driver (initially, CLC SiP driver highlighting logic-DRAM integration, DARPA MSP (Boeing STAP)) u Interfaces and standards (“infrastructure”) for design process s Internal to flows and methodologies s External: down (manufacturing variability models, mask flow handoff, cluster tool abstractions, … ) or up (IO cells, signaling standards, logic, system-level, …) s Measurement and quantification of design quality, design productivity

abk Concrete Outcomes u Task 1: Living Roadmap (from applications through ITRS technologies) s Cost-aware s Gaps  research + tool needs t Manufacturing handoff, die-package interface, variability, global signaling, synchronization, power delivery, robustness, … s GTX grows into a system-level analysis tool that is validated with design drivers u Task 2A: Develop SiP implementation platforms s Platform-specific tools and roadmapping u Task 2B: High-End (“Radar on a Chip”) Driver s Demonstration vehicle for overall GSRC methodology and CLC SiP-specific tools s Driver scaling + extrapolation s Integration paths for GSRC’s and other design methodologies u Task 3: Design process infrastructure s Design data models and interfaces  current enablers, future standards s Reusable, composable solvers  rapid flow synthesis/optimization s Concrete realizations of GSRC and other methodologies t with metrics and automated evaluators (bX)

abk Working Sessions u Goals s Drivers: Which ones? How they unify GSRC activities? Key research gaps? Roadmaps of functional requirements, technology showstoppers s Roadmapping: PED and Reliability s Design Infrastructure: OpenAccess data model and extensions; mini-flows and benchmarking (placement focus) u Today 10:30 – noon (joint with PED and Reliability) s CLC SIP and MSP, Radar-on-Chip Driver (Dai) s PicoRadio (PicoNode) Driver (Rabaey) u Today 1:00 – 2:30 pm s Home Gateway Driver (Kulkarni, Keutzer, Hwu) – brainstorming session u Today 3:00 – 4:00 pm s Roles of Drivers in new GSRC

abk Driver Discussions u Which ones? u How do they unify GSRC activities? u Key research gaps? u Roadmaps of functional requirements, technology showstoppers u Today 10:30 – noon (joint with PED and Reliability) s CLC SIP and MSP, Radar-on-Chip Driver (Dai) s PicoRadio (PicoNode) Driver (Rabaey) s MicroLab (alternative space) (Gupta) u Today 1:00 – 2:30 pm s Home Gateway Driver (Kulkarni, Keutzer, Hwu) – brainstorming session u Today 3:00 – 4:00 pm s Roles of Drivers in new GSRC

abk Driver Discussions u A DRIVER IS: s A concrete design for a specific application s (Lots of $, very few papers ) u WHAT (D&T) PROBLEM IS THE DRIVER TRYING TO GET US TO SOLVE? s Continuation of the Moore’s Law for COST s Scalability of design or its infrastructure s Conceptualization (modeling, representation, validation) of systems s Unreliability and Unpredictability at component level s (Validation should be on this list, but how exactly are the drivers such as Radar- On-Chip driving validation?) s (Should Power be a first-class citizen?) s (N.B.: “Mixed-*” is mostly implicit in Conceptualization) u WHAT ARE DELIVERABLES ASSOCIATED WITH A DRIVER? s Design data (spec, arch, netlist, implementation, simulation, verification) and hardware s Tools

abk Driver Discussions u Axes for Drivers: s Metrics: heterogeneity, performance, power, size, reliability/RAS, cost s Impact: intrinsic value, interest (DARPA? HP/IBM/? Or Bechtel/PGE/?), technology leading edge s Synergy: semiconductor technologies, bridges within GSRC, package, system u System-Level vs. Fabric/Block Level s Application-level vs. implementation-level challenges s Bottom-up super-components (= top-down subsystems) that enable system: are these created by GSRC or C2S2? u Candidates s Batteryless t Ambient embedded networked sensing (= proxy for “next-gen”) t PicoNode, LabOnChip, MICA, SmartDust s High-performance computing t SIP / stacking: Radar On Chip: STAP DSP + Memory integration, CLC-SIP physical platform t General-purpose computing (500 5GHz MIPS cores on chip) t Utility computing (data center

abk Driver Discussions u Drivers + Infrastructure = third dimension s Are we picking drivers as a minimum-size cover, or are we picking drivers as “impactful”? Need to bound the goals, scope, … of this discussion s Communication-based, soft systems s DFX: Test, Verification, Power, Reliability, … u Other s Logistics t Leveraging (“how we do it now”), not building (rather, “hypothesis testing”) t Common access s Need a driver taxonomy + metrics: access/interfacing, heterogeneity, etc. s Links: OpenGIS.org, Security (SEC Disaster Recovery + Business Continuance), Recover-Oriented Computing, … s Home Gateway: How does drive VLSI and IC design? s What criticality is being overcome by spending $$$ on this driver?

abk PD Open Problems (Payman and Amir) u Incremental u Combined Placement and Floorplanning s locks solution into a bad subspace s Timing is a constraint (not an objective); WL is an objective s Problem = lack of understanding of interrelationships between different objectives, e.g., timing, area (fixed-die) and congestion t N.B.: WL may not really be an objective: it is a proxy for congestion (area) s Issue of capturing timing in top-down partitioning-based placement (partitioning is net-based; timing is path-based) u How is SI solved at placement? u IR drop placement? IR drop has impact on timing and reliability and hence important u Variability-aware placement?

abk PD Open Problems (Payman and Amir) u Thermal placement (not just dynamic power minimization) s Given activities of all gates, find a placement to minimize a linear combination of dynamic power and maximum thermal variation u Hierarchy? s Probably moving to u Datapath-based (timing-constrained) placement s People have tried but have not achieved notably better results s 2 literature from late 1980’s: Ebeling et al. subgraph isomorphism, Odawara/Szymanski/Nijssen-Jess/Varadarajan-Arikati on regularity extraction

abk PD Open Problems (Payman and Amir) u Power implications (voltage islands) s Chuck also mentions this s Clock gating s Multi-Vdd islands: granularity of several hundred cells (?) – 1-2 rows min in V, stripe pitch min in H s Ground islands (shutdown of blocks keeping memory partially powered up) s Cf. Amir’s work at Northwestern ~1995 u Placement for BIST (check with Tim Cheng et al.) u Signal Integrity Issues (crosstalk handling at floorplan and placement) u Clock distribution u Suggestion: Single-width, single-pitch cell layout, synthesis, place and route flow: WOULD BE HEROES !!! (PhasePhirst!, SCAAM, etc. == next-generation lithography proposals, all of which depend on “hyper-resolution” (“2-beam imaging”)  basically, only one direction and one pitch will print (the layout is a subset of a grating). Goal: C.A.D. people should prove a one-time, bounded hit on Moore’s Law (e.g., 30% density) but then scalability of SP&R thereafter. u X, Y Architectures March 5 th EE Design ? u Design for Variability u Backend Process Optimization s Complex objective: marketing, methodology, integration s Marketing: BEOL should be optimized for many designs (derivatives, etc.) – range of size, frequency, etc. s Methodology: Crosstalk, IR drop, routing density, etc. t Statistical information : %WL per layer, %designs having X #gates, Y MHz, s Integration: cost of fabrication (e.g., AR limits, low metal-layer count, #layers, thickness (mfg throughput, pitch LBs from AR limits, …))

abk Working Sessions u Friday parallel session #1: Roadmapping s 9:00 – 11:00am (joint with PED and Reliability) s Background (Energy, Reliability, Variability) s Panel: PED Roadmapping Needs and Research Gaps s 11:00am – noon s Roadmapping of Process Variability, Cost Optimizations u Friday parallel session #2: Infrastructure, Benchmarking s 9:00 – 10:00am s BX and Benchmarking Status s 10:00am – 11:00am s Placement-Centered Directions (Mini-Flows, New Problems) s 11:00am – noon s Concrete steps with OpenAccess u Friday 1:30 – 2:30pm s Discussion of C.A.D. Roles in the “New GSRC”: collaborations, projects, milestones