January, 2003CMS Ecal MGPA Design Review1 MGPA design review architecture overview and specifications detailed architecture top level functional block diagram CSA stage VI stage Differential O/P stage CAL circuit noise: sources and simulations process simulations – whole circuit (including power supply – 10%, temperature variations) linearity pulse shape matching gain noise I/P interface input APD, VPT (transmission line effects) power and PSR miscellaneous issues: bond lead inductance, protection, layout specifications review outstanding issues

January, 2003CMS Ecal MGPA Design Review2 MGPA specifications ParameterBarrelEnd-Cap fullscale signal60 pC16 pC noise level [electrons]10,000 electrons3,500 electrons noise level [C]1.6 fC0.56 fC input capacitance~ 200 pF~ 50 pF output signals to match ADCdifferential 1.8 V, +/ V around Vcm = (Vdd-Vss)/2 = 1.25 V gain ranges1, 6, 12 gain tolerance (each range)+/- 10 % linearity (each range)0.1 % fullscale pulse shaping (impulse response)40 nsec CR-RC channel/channel pulse shape matching < 1 % Vpk Vpk-25ns Vpk-25ns/Vpk matches to 1% across gain ranges

January, 2003CMS Ecal MGPA Design Review3 external components define CR and CSA gain external components define RC V/I gain resistors offset & CAL pulse generation I2C interface offset adjust MGPA – architecture overview diff. O/P

January, 2003CMS Ecal MGPA Design Review4

January, 2003CMS Ecal MGPA Design Review5 CSA I/P stage conventional folded cascode maximise use of available dynamic range resistor to VDD -> I/P device Vs ~ 1V => I/P and O/P as close as poss. to VSS note output -> PMOS source followers with ~0.5V VGS ext. components define gain and O/P decay time (40 ns) choose to suit barrel/endcap Cpf/Rpf = 33pF/1.3k (barrel) or 10pf/4k (endcap) => max signal accommodated (~ 1V) with min. pile-up input device dimensions big gm needed for low O/P risetime (Cdet~200pF) 30,000/0.36 -> Cgs ~60 pF, gm~.3A/V bias current magnitudes (externally defined) for big I/P device gm (see above) slew rate at output node bias transistor dimensions avoid minimum length keep gm low (noise) but need low Vdsat

January, 2003CMS Ecal MGPA Design Review6 CSA O/P simulation (barrel case) nominal process parameters Cpf/Rpf = 33pF/1.2k input capacitance 200 pF signal injected at 25 ns 0 -> 60 pC in 2pC steps 10 ns arrival time to simulate scintillation decay time resulting pulse peaks at 47 ns (22ns injection -> pk) ~ 1.1 Volt max amplitude swing

January, 2003CMS Ecal MGPA Design Review7 CSA O/P simulation (end-cap case) Cpf/Rpf = 10pF/4k input capacitance 50 pF signal injected at 25 ns 0 -> 16 pC in 1pC steps 10 ns arrival time to simulate scintillation decay time resulting pulse peaks at 48 ns => 23ns injection -> pk ~ 1.0 Volt max amplitude swing CSA O/P pulse shape ~ independent of whether barrel or endcap

January, 2003CMS Ecal MGPA Design Review8 VI stage design choices governed by: linearity, noise considerations, supply current requirements (not excessive), need to produce current output (high O/P impedance) to drive diff. O/P stage Rgain gives good linearity acceptable noise (later) s.f. and cascode currents all derived from one current source cascode gate voltage derived from preamp I/P ensures minimum DC voltage across Rgain s.f. and cascode widths and drain currents for large gm (note Rgain values relatively small) IDS different for different gain stages chosen to get linearity within spec. trade-off linearity/power rangeRgain [ohms]Ibias [mA] high1722 mid4116 low2409 RC coupled (external)

January, 2003CMS Ecal MGPA Design Review9 VI stage simulation waveforms (nominal process parameters) low gain channel signal: 0 -> 60 pC in 6 pC steps source follower O/P cascode I/P cascode O/P 1.1V 2.2V

January, 2003CMS Ecal MGPA Design Review10 ADC I/P signal range: +/ V around Vcm (1.25V) O/P RC termination sets shaping time const. 200 ohms compromise between “low-ish” O/P impedance and DC quiescent current 40 nsec requires 100 pF differential (2.5 pF/nsec) or 200 pF each O/P to Vcm (5 pF/nsec) programmable offset adjust to each channel Differential O/P stage single ended current in -> differential current out

January, 2003CMS Ecal MGPA Design Review11 Lowest gain channel – differential O/P stage signals signals: 0 – 60 pC, 2 pC steps V CM = 1.25 V

January, 2003CMS Ecal MGPA Design Review12 Higher gain channels – saturation effects (still 0 – 60 pC, 2 pC steps) highest gain range middle gain range

January, 2003CMS Ecal MGPA Design Review13 MGPA output: (out+) – (out-) 0 – 60 pC, 2 pC steps highest (red) and mid (blue) gain ranges saturate lowest (green) well-behaved

January, 2003CMS Ecal MGPA Design Review14 CAL circuit

January, 2003CMS Ecal MGPA Design Review15 CAL circuit simulation 10pF 1nF DAC value e.g. 100mV MGPA I/P 10k Rtc Rtc:0 ->10  Highest gain channel O/P for 1 pC input signal Can use Rtc to simulate real signal risetime external components

January, 2003CMS Ecal MGPA Design Review16 Noise C IN v FET 2 v Rpf 2 R pf charge amp. s.f. RGRG diff. O/P gain stage C pf V CM CICI RIRI transconductance gain stage ENC due to charge amp. noise sources: R pf : note: R pf constrained by C pf (R pf C pf =  = 2R I C I = 40 nsec. ) -> 4900 electrons (barrel) -> 2700 electrons (endcap) I/P FET:(C TOT = C IN + C FET + C pf ) -> 1800 electrons (barrel, C IN =300pF ( )) -> 660 electrons (endcap, C IN =112pF ( )) =>no strong dependence on C IN K 1  R pf 1/2 K 2 v FET C TOT  1/2 i CFET 2 i RG 2

January, 2003CMS Ecal MGPA Design Review17 Noise C IN v FET 2 v Rpf 2 R pf charge amp. s.f. RGRG diff. O/P gain stage C pf V CM CICI RIRI transconductance gain stage ENC due to transconductance stage sources: R G -> Cpf dependence because relative magnitude depends on charge amp gain. Keep R G as small as poss. but has to vary for different gain stages Cascode FET -> C pf and R G dependence V/I stage noise sources become more important for lower gains (bigger R G ) i CFET 2 i RG 2 RG RG  1/2 K 3 C pf gm gm  1/2 K 4 C pf R G

January, 2003CMS Ecal MGPA Design Review18 Simulated noise dependence on gain these results are for final gain range spec. (1, 6, 12), nominal process parameters and VDD, T gain resistor noise dominates for lowest gain range numbers in red exceed 10,000 (3500) but signal size means relative contribution to overall energy resolution less significant (see GainRGRG signal range (barrel) [pC] Noise (barrel) [electrons] signal range (endcap) [pC] Noise (endcap) [electrons] – – – – , –

January, 2003CMS Ecal MGPA Design Review19 Process and environment simulations Process parameters: sigma (length,VT): 0, +/- 1.5 np mismatch: nom, +/- 3 sigma values Supply Voltage: (+/- 5%) 2.375, 2.5, 2.625(not yet done) Temperature:-10, 25, 75 simulation results here for 1, 5, 10 gain ratios (not latest 1, 6, 12) simulations: transient: signals: 0 -> fullscale in 10 steps, for each gain range look at: linearity |linearity|< 0.1% fullscale pulse shape matching V[pk-25ns]/V[pk] matches to 1% for all signals within gain ranges across gain ranges noise & gain

January, 2003CMS Ecal MGPA Design Review20 simulation example signals: 0 -> ~ fullscale in 10 steps for all 3 gain ranges for a given set of process parameters and environment variables (VDD, T) look for: linearity within gain ranges (+/- 0.1% fullscale) 6 pC, 12 pC, 60 pC pulse shape matching for all sizes of signals within gain ranges and across gain ranges (+/- 1%)

January, 2003CMS Ecal MGPA Design Review21 Linearity results: VDD = 2.5V, T=25 Linearity definition: peak pulse ht. – fit (to pk pulse ht) X100 fullscale signal results here for: sigma = -1.5, 0, 1.5 np mismatch = -1, 0, 1 27 curves: 9 for each gain range

January, 2003CMS Ecal MGPA Design Review22 Linearity results: VDD = 2.375V (- 5%), T=25 results here for: sigmanp mismatch curves: 5 for each gain range

January, 2003CMS Ecal MGPA Design Review23 Linearity results: VDD = 2.375V (- 5%), T=75 results here for: sigmanp mismatch curves: 4 for each gain range

January, 2003CMS Ecal MGPA Design Review24 Linearity results: VDD = 2.375V (- 5%), T=-10 results here for: sigmanp mismatch curves: 4 for each gain range

January, 2003CMS Ecal MGPA Design Review25 Pulse shape matching results: VDD = 2.5V, T=25 Pulse shape matching definition: Pulse Shape Matching Factor PSMF=V(pk-25ns)/V(pk) Ave.PSMF = average for all signal sizes and gain ranges, for a particular set of process parameters Pulse shape matching = [(PSMF-Ave.PSMF)/Ave.PSMF] X 100 results here for: sigma = -1.5, 0, 1.5 np mismatch = -1, 0, 1 27 curves: 9 for each gain range

January, 2003CMS Ecal MGPA Design Review26 Pulse shape matching results: VDD = 2.375V (- 5%), T=25 results here for: sigmanp mismatch curves: 5 for each gain range

January, 2003CMS Ecal MGPA Design Review27 Pulse shape matching results: VDD = 2.375V (- 5%), T=75 results here for: sigmanp mismatch curves: 4 for each gain range

January, 2003CMS Ecal MGPA Design Review28 Pulse shape matching results: VDD = 2.375V (- 5%), T=-10 results here for: sigmanp mismatch curves: 4 for each gain range

January, 2003CMS Ecal MGPA Design Review29 gain dependence on process params histogram peak pulse heights for fullscale (6 pC) signal for highest gain range other gain ranges behave similarly VDD=2.5V, T=25 VDD=2.375V, T=25 VDD=2.375V, T=75 VDD=2.375V, T= -10 peak pulse height for 6 pC signal [V]

January, 2003CMS Ecal MGPA Design Review30 histogram noise dependence on process params, VDD &T

January, 2003CMS Ecal MGPA Design Review31 End-cap VPT interface coax Cdet I(t) MGPA CSA O/P chip O/P I(t) current source with 10 ns decay time Cdet = 5 pF (2 pF + stray) coax = RG 179 (thin 50 ohm) 75 cm long some ringing observable at CSA O/P smoothed out at chip O/P

January, 2003CMS Ecal MGPA Design Review32 Barrel APD interface coax Cdet I(t) MGPA CSA O/P chip O/P I(t) current source with 10 ns decay time Cdet = 160 pF (2 APDs) coax = RG 179 (thin 50 ohm) – 30 cm long some ringing observable at CSA O/P once again smoothed out at chip O/P would be better to have more accurate interconnection model

January, 2003CMS Ecal MGPA Design Review33 Power 2.5 V Stagecurrent [mA]bias cctno.power[mW] CSA High gain VI Mid-gain VI Low gain VI Diff O/P Total503

January, 2003CMS Ecal MGPA Design Review34 PSR rejection - preliminary 0 dB -20 dB -40 dB -60 dB k1M swept frequency sine-wave superimposed on VDD resulting output on high gain channel O/P [(out+) – (out-)] high frequency rejection due to RC filtering of power rail (RC = 1  x 10  F) some rejection at DC but gain at ~ 100 Hz Hz

January, 2003CMS Ecal MGPA Design Review35 PSR rejection improvement 0 dB -20 dB -40 dB -60 dB k1M replace “resistor to rail” biasing by ideal current sources (CSA and VI stages) 100 Hz “bump” removed DC rejection the same more detailed study needed here – hope for further improvement Hz

January, 2003CMS Ecal MGPA Design Review36 Any effect of bond-wire inductance? model by inserting inductances between external decoupling and internal circuit nodes L=0,2,4,6 nH high gain range signal = 5 pC effect just visible no sig. effects on performance

January, 2003CMS Ecal MGPA Design Review37 Conceptual layout 80 pin package – may -> 100 CAL circuit included spare pins available for I2C test & reset extra power segmented approach minimise crosstalk between different gain stages multiple power pads all bias lines decoupled diff. O/Ps separated layout (chip and hybrid) needs care different stray capacitance -> different pulse shapes/gain range) internal gain resistor +/- 10 % tolerance

January, 2003CMS Ecal MGPA Design Review38 MGPA specifications review ParameterBarrelEnd-Cap fullscale signal60 pC16 pC noise level [electrons]10,000 electrons3,500 electrons noise level [C]1.6 fC0.56 fC input capacitance~ 200 pF~ 50 pF output signalsdifferential 1.8 V, +/ V around Vcm = (Vdd-Vss)/2 = 1.25 V gain ranges1, 6, 12 gain tolerance (each range)+/- 10 % linearity (each range) +/- 0.1 % fullscale pulse shaping (filtering)40 nsec CR-RC channel/channel pulse shape matching < 1 % technology spec. for resistors used need to tweak OK for mid and high gain ranges (low gain not a problem) OK

January, 2003CMS Ecal MGPA Design Review39 Outstanding issues tweak the gain resistor values (trivial - don’t expect any adverse consequences) choose CAL circuit DAC resistor values (trivial) PSR – could adjust CSA, VI stage bias cctry to improve (needs some thought) needs to be supply independent – use bandgap or VT referenced current sources (existing designs) channel offset generation make supply independent check O/P stage in conjunction with ADC I/P stage (should be done)