CML CML CS 230: Computer Organization and Assembly Language Aviral Shrivastava Department of Computer Science and Engineering School of Computing and Informatics Arizona State University Slides courtesy: Prof. Yann Hang Lee, ASU, Prof. Mary Jane Irwin, PSU, Ande Carle, UCB

CML CMLAnnouncements Project 3 –Due October 19, 2009 Midterm –Thursday, October 22, 2009 –Contents MIPS ISA and Programming Function calls and register conventions Assembling MIPS Instructions 2’s complement number system FP number system Finals –Tuesday, Dec 08, 2009

CML CML Computer Organization We have leaned the ISA of the processor till now –Given an algorithm, express it in terms of the processor ISA Instruction Set Architecture software hardware

CML CML  High-level language program (in C) swap (int v[], int k)...  Assembly language program (for MIPS) swap: sll $2, $5, 2 add $2, $4, $2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31  Machine (object) code (for MIPS) Below the Program C - Compiler Assembler

CML CML Working of Computer Processor Control Datapath Memory Devices Input Output

CML CML Input Device Inputs Object Code Processor Control Datapath Memory Devices Input Output

CML CML Object Code Stored in Memory Processor Control Datapath Memory Devices Input Output

CML CML Processor Fetches an Instruction Processor Fetches an Instruction Processor Control Datapath Memory Devices Input Output Processor fetches an instruction from memory

CML CML Control Control Decodes the Instruction Control Decodes the Instruction Processor Datapath Memory Devices Input Output Control decodes the instruction to determine what to execute

CML CML Datapath Executes the Instruction Processor Control Datapath Memory Devices Input Output contents Reg #4 ADD contents Reg #2 results put in Reg #2 Datapath executes the instruction as directed by control

CML CML Update the PC, and continue Processor Control Datapath Memory Devices Input Output Fetch DecodeExecute

CML CML Output Data Stored in Memory Processor Control Datapath Memory Devices Input Output At program completion the data to be output resides in memory

CML CML Output Device Outputs Data Processor Control Datapath Memory Devices Input Output

CML CML MIPS ISA to Implement Arithmetic Instructions –Add, sub, AND, OR, and slt (R-type) Memory access instructions –LW, and SW (I-type) Branch instructions –Beq(I-type) Jump instructions –J(J-type)

CML CML MIPS Machine Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch Shift left Jump 32 Instr[25-0] 26 PC+4[31-28] 28

CML CML Build a MIPS Processor Today – Build the ALU –Support all the Arithmetic/Logic operations 32 ALU control lines result a b ALU ALU Control LinesFunction 0000AND 0001OR 0010add 0110subtract 0111Set on less than 1100NOR

CML CML ALUOp and ALU control bits Instruction Opcode ALUOpInstruction operation Funct field Desired ALU action ALU control input LW00Load wordXXXXXXadd0010 SW00Store wordXXXXXXAdd0010 Beq01Branch equalXXXXXXSubtract0110 R-type10Add100000Add0010 R-type10Subtract100010Subtract0110 R-type10AND100100AND0000 R-type10OR100101OR0001 R-type10Set on less than101010Set on less than0111

CML CMLImplementation Truth table for 4 ALU control bits

CML CML Building a 1-bit Binary Adder S = A xor B xor carry_in carry_out = (A and B) or (A and carry_in) or (B and carry_in) 1 bit Full Adder A B S carry_in carry_out How can we use it to build a 32-bit adder? How can we modify it easily to build an adder/subtractor? ABcarry_incarry_outS

CML CML Building 32-bit Adder Just connect the carry-out of the least significant bit FA to the carry-in of the next least significant bit and connect... Ripple Carry Adder (RCA) –advantage: simple logic, so small (low cost) –disadvantage: slow and lots of glitching (so lots of energy consumption) 1-bit FA A0A0 B0B0 S0S0 c 0 =carry_in c1c1 1-bit FA A1A1 B1B1 S1S1 c2c2 A2A2 B2B2 S2S2 c3c3 c 32 =carry_out 1-bit FA A 31 B 31 S 31 c 31...

CML CML Building 32-bit Adder/Subtractor Remember 2’s complement is just –complement all the bits –add a 1 in the least significant bit A 0111  0111 B  bit FA S0S0 c 0 =carry_in c1c1 1-bit FA S1S1 c2c2 S2S2 c3c3 c 32 =carry_out 1-bit FA S 31 c A0A0 A1A1 A2A2 A 31 B0B0 B1B1 B2B2 B 31 add/subt B0B0 control (0=add,1=subt) B 0 if control = 0, !B 0 if control = 1

CML CML Logic Operations Logic operations operate on individual bits of the operand. $t2 = 0… $t1 = 0… and $t0, $t1, $t2$t0 = or $t0, $t1, $t2$t0 = xor $t0, $t1, $t2$t0 = nor $t0, $t1, $t2$t0 = How do we expand our FA design to handle the logic operations - and, or, xor, nor ? 0… … … …

CML CML A Simple ALU Cell 1-bit FA carry_in carry_out A B add/subt result op

CML CML Tailoring the ALU to the MIPS ISA Need to support the set-on-less-than instruction ( slt ) –remember: slt is an arithmetic instruction –produces a 1 if rs < rt and 0 otherwise –use subtraction: (a - b) < 0 implies a < b Need to support test for equality ( beq ) –use subtraction: (a - b) = 0 implies a = b Need to add the overflow detection hardware

CML CML Modifying the ALU Cell for slt 1-bit FA A B result carry_in carry_out add/subtop add/subt less

CML CML ALU for slt 0 0 set  First perform a subtraction  Make the result 1 if the subtraction yields a negative result  Make the result 0 if the subtraction yields a positive result tie the most significant sum bit (sign bit) to the low order less input

CML CML ALU for Zero + A1A1 B1B1 result 1 less + A0A0 B0B0 result 0 less + A 31 B 31 result 31 less set  First perform subtraction  Insert additional logic to detect when all result bits are zero zero... add/subt op Note zero is a 1 when result is all zeros

CML CML Overflow Detection Overflow: the result is too large to represent in the number of bits allocated On your own: Prove you can detect overflow by: –Carry into MSB xor Carry out of MSB – –4 –

CML CML Modifying the ALU for Overflow + A1A1 B1B1 result 1 less + A0A0 B0B0 result 0 less + A 31 B 31 result 31 less set  Modify the most significant cell to determine overflow output setting  Disable overflow bit setting for unsigned arithmetic zero... add/subt op overflow

CML CML Shift Operations Also need operations to pack and unpack 8-bit characters into 32- bit words Shifts move all the bits in a word left or right sll $t2, $s0, 8 #$t2 = $s0 << 8 bits srl $t2, $s0, 8 #$t2 = $s0 >> 8 bits Such shifts are logical because they fill with zeros op rs rt rd shamt funct

CML CML Shift Operations An arithmetic shift ( sra ) maintain the arithmetic correctness of the shifted value (i.e., a number shifted right one bit should be ½ of its original value; a number shifted left should be 2 times its original value) –so sra uses the most significant bit (sign bit) as the bit shifted in –note that there is no need for a sla when using two’s complement number representation sra $t2, $s0, 8 #$t2 = $s0 >> 8 bits The shift operation is implemented by hardware (usually a barrel shifter) outside the ALU

CML CML MIPS Machine Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch Shift left Jump 32 Instr[25-0] 26 PC+4[31-28] 28

CML CML Yoda says… Use your feelings, Obi-Wan, and find him you will