Verilog-A models of building blocks E. Atkin, Y. Bocharov, A. Gumenjuk, A.Kluev, A. Simakov (MEPHI), A.Voronin (SINP MSU)

11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt Outline (part 1) ADC Verilog models: Basic model features Designed models Simulation time “Black-box” model Behavioral model Model test setup Model test examples 11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt

11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt Outline (part 2) CSA Background CSA macromodel Frequency domain (AC) model – small signal one Noise model Input transistor Time domain (TRAN) model – large signal one Leakage current compensation Both polarities of input pulses Summary 11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt

The two pipelined 9 bit ADC Verilog models are presented ADC models (part 1) A. Gumenjuk, Y. Bocharov, A. Simakov The two pipelined 9 bit ADC Verilog models are presented

The basic model features Range of accuracy – how does model performance satisfy the reality? Detailing degree – how many parameters are taken into account? Used description tools – what simulators are needed to perform model analysis? Required machine resources – how much time is needed to simulate the model? 11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt

11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt The designed models “black-box” Behavioral level Transistor level Extracted level accuracy Low Medium High Highest detailing tools Verilog-A Verilog-A / Verilog spectre (Verilog) spectre machine resources excessive 11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt

Required simulation time ADC models have been simulated on a 3.2 GHz 1Gb RAM Pentium 4 processor for receiving 4096 FFT points “black-box” Behavioral level Transistor level Extracted level Simulation time 8 s 1m 30s 10 h several weeks! 11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt

11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt The “black-box” model ADC is modeled as “black box”, that demonstrates the same functionality as a real one We describe only: The ideal sampling and quantization ADC functions The actual conversion latency 11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt

The “black-box” model (cont) ADC is modeled as “black box”, that demonstrates the same functionality as a real one The model features: The model is very simple and fast for simulation The model is very useful for early system simulation The model is ideal and doesn’t take into account the real ADC performance 11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt

Verilog-A as an extension of Spice* * D.FitzPatrick, I.Miller. Analog_Behavioral_Modeling_With The_Verilog-A_Language. Kluwer Academic Publisher, 2003 11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt

The behavioral model ADC is modeled using a set of Verilog-A and Verilog blocks 2-bit flash ADC 1.5-bit stages Sample-and-Hold circuit Verilog-A Verilog-A Digital delay and RSD Verilog-A Verilog 11th CBM Collaboration Meeting, 26.02.08, GSI, Darmstadt

The behavioral model (cont) The model takes into account a set of static block parameters and inaccuracy of ADC stage, such as: OpAmp performance (dc gain, bandwidth, offset) Comparator performance (resolution, offset) Stage capacitor mismatches Reference voltage inaccuracy 11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt

The model test setup Verilog-A The ADC model 9 bit digital output Ideal 9 bit DAC analog equivalent of ADC result Differential sine voltage source 11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt

11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt The model test example 1 The simulated output spectrum of a 9-bit 20 MSps ADC model at Nyquist input frequency 9.77MHz input signal SNR = 56.0 dB SFDR = 68.3 dB ENOB = 9.0 bit 11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt

11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt The model test example 2 The simulated output spectrum with a normally distributed capacitor mismatch SNDR = 55.4 dB SFDR = 67.6 dB ENOB = 8.9 bit SNDR = 35.7 dB SFDR = 36.0 dB ENOB = 5.6 bit σ=0.1% σ=10% 11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt

E. Atkin, A. Kluev (MEPHI), A.Voronin (SINP MSU) CSA models E. Atkin, A. Kluev (MEPHI), A.Voronin (SINP MSU)

Starting point and background CSA prototype of 2005 (UMC 0.18, IC 5.1.41 CDBA) All we have shifted into IC 6.1 OA, but… At the moment there are two general problems: Officially UMC 0.18 um DKs can not be used with Cadence OA No MonteCarlo models for 0.18 um technology 11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt

Prototype CSA versus CBM-XYTER specs Channel size (w x l), µm 50 x 1000 40 x 1000 max (?) No. of chs. 8 100-200 (for ex.128 typ+2 dummies) Detector capacitance, pF 0-100 0-30 ENC, el. @ 30pF 2250 (no shaper) (SNR=10 @ 1 mip) 800 DC coupling, leakage current compensation Yes Polarity Both Input PMOS (NMOS ?), µm 600 x 0.18 @ 360 µA W↑ => noise↓ Power consumption, mW (current consumption, µA) ~0.7 typ (550 @ -0.9V 180 @ +0.9V) <1 CSA rise time, @10%-90%, ns 20 @20pF 100@100pF -- Output noise, µV rms 400 11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt

2 reasons of the need for higher levels of abstraction to describe analog circuits 1. A need for higher-level models, describing the pin-to-pin behaviour of the circuits, rather than the internal structural implementation 2. A need to allow a full simulation of the entire mixed-signal design, being usually a computationally too complex

Different Analog Hardware Description Levels G.Gielen, R. Rutenbar Computer-Aided Design of Analog and Mixed-Signal Integrated Circuits Proc. of IEEE, vol.88, no.12, 2000 11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt

Description Analyses Large-signal module definition Time domain – main type DC transfer curve AC small-signal Other…

Parameters of interest Gain Integral Noise Large signal non-linearity DC accuracy Power consumption External interfaces to detector and back-end Crosstalks Detailed noise (1/f, parallel, serial) Programmability (peaking time, biasing) Detailed substitution circuit for multistrip (including double sided) detector interface

Model elaboration flow Transistor circuit Model elaboration flow Qualification of parameters and characteristics Higher Lower Yes Functional modelling No Yes Simulation time / complexity Behaivioral modelling Type of model Abstraction level No Yes Macro modelling Lower Higher No

Feedback splitting Gain=800 F-3db=1e5 rmsNoise=400e-6 Gm=1uA/V F-3db=1

AC small-signal model (simplified example) `include "discipline.h" Endmodule `include "constants.h" module res1(vp, vn); module cap2(vp, vn); inout vp, vn; module vccs(iout_p, iout_n, vin_p, vin_n); electrical vp, vn; parameter real r = 270K; parameter real c = 200f; input vin_p, vin_n; output iout_n, iout_p; electrical iout_n, iout_p, vin_p, vin_n; V(vp, vn) <+ r*I(vp, vn); parameter real gm = 3.8m; module cap1(vp, vn); module preamp(in,out,gnd); analog input in; I(iout_p, iout_n) <+ gm*V(vin_p, vin_n); output out; parameter real c = 3p; inout gnd; endmodule electrical in, out, gnd; module vcvs(vout_p, vout_n, vin_p, vin_n); I(vp, vn) <+ ddt(c*V(vp, vn)); vccs VCCS(.vin_p(in),.vin_n(gnd),.iout_p(net_inter),.iout_n(gnd)); output vout_p, vout_n; module res2(vp, vn); res1 R1(.vp(net_inter),.vn(gnd)); electrical vout_p, vout_n, vin_p, vin_n; cap1 C1(.vp(net_inter),.vn(gnd)); vcvs VCVS(.vin_p(net_inter),.vin_n(gnd),.vout_p(out),.vout_n(gnd)); parameter real r = 1G; parameter real gain = 0.79; res2 R2(.vp(out),.vn(in)); V(vout_p, vout_n) <+ gain*V(vin_p, vin_n); cap2 C2(.vp(out),.vn(in)); 11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt

AC Noise model (simplified) E1noise – sum of leakage currents, existing on the preamp input ~eI (shot noise) E1noise serial noise 1/F+4kTReq Enoise of R13 4kTR13 I2noise shot parallel noise of FB (1/F?) Enoise_fb noise of active FB 1/F^n+4rTRact Isig – signal source 11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt

Large signal model (example) Modeled are: Gain, Small-signal AC response Pos. and neg. clamps, Consumption 11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt

Required simulation time CSA models have been simulated on a 2.4 GHz 1.5Gb RAM Pentium 4 processor for passing 1us TRAN analysis “black-box” Behavioral level Transistor level Extracted level Simulation time 20 ms 30 ms 100 ms not modeled 11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt

11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt Summary and Outlook Written are, but not shown here, Veilog-A code for relevant blocks (CSA and ADC) Designed are very simple Verilog-A ADC and CSA models for fast System simulation Also designed are behavioral ADC and CSA models, taking into account some static inaccuracies It is planed to advance the models for raising their accuracy (e.g. considering the dynamic ADC nonlinearity, CSA large signal behavior and detailed noise modeling) Also it is planed to prototype the ADC. GDSII file is ready and waiting for the MPW (miniASIC) chance. 11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt