台大電機系 陳信樹副教授 National Taiwan University Department of Electrical Engineering 設計於深次微米 CMOS 製程之功率感知高速類比數位轉換積體電路 (Power-Aware High-Speed ADC in Deep Submicron CMOS) 文化大學電機系 2011 年先進電機電子科技研討會

NTUEE ; Mixed-Signal IC Lab 陳信樹 Outline Motivation High-speed ADC IC design example Digitally-assisted algorithm and architecture Circuit implementation Experimental results Summary 2

NTUEE ; Mixed-Signal IC Lab 陳信樹 High-Speed ADC Applications Ref [1] 3

NTUEE ; Mixed-Signal IC Lab 陳信樹 Power-Aware High-Speed ADC Trends Power / Energy  Higher resolution requires more energy to achieve. Speed / Bandwidth  Resolution and speed are trade-offs. Bottleneck  SAR architecture saves power and chip area, but speed is limited by its conversion algorithm.  Pipelined architecture achieves high speed by concurrent operations, but OPAs consume considerable power. Digitally assisted ADCs  Digitally assisted algorithm alleviates analog circuit requirement; therefore, it takes advantages of advanced processes to trade little digital power to gain the benefits from analog part. 4

NTUEE ; Mixed-Signal IC Lab 陳信樹 High-Speed ADC Energy vs. SNDR Energy is proportional to resolution (SNDR). FOM (Power / (Sample rate * 2 ENOB )) is an indicator to compare different ADC designs. State-of-the-art ADC designs approach 10fJ/c.s. Current world record is 4fJ/c.s. Ref [2] 5

NTUEE ; Mixed-Signal IC Lab 陳信樹 High-Speed ADC Bandwidth vs. SNDR Bandwidth is inverse proportional to resolution (SNDR). State-of-the-art high-speed high-resolution ADCs are limited by clock jitter around 0.1psrms. Ref [2] 6

NTUEE ; Mixed-Signal IC Lab 陳信樹 Experiment 1 - Low-Power High-Speed Two-Step ADC Rearrange the timing of two-channel MDACs and apply a self-timing technique to alleviate comparator comparison time and charge injection disturbance Slightly increases CADC accuracy to ease OPA signal swing design Ref [3] Technology0.13μm Resolution6-bit Active area0.16mm 2 Supply voltage1.2V Sample rate1-GS/s SFDR (F SNR (F SNDR (F Power49mW FoM1.24pJ/c.s. 7

NTUEE ; Mixed-Signal IC Lab 陳信樹 Relieve MSB accuracy requirement by the sub-range concept with overlapping Reduce total input capacitance by using the double-unit- sized coupling-capacitor Ref [4] Experiment 2 - Low-Power High-Speed Sub-range SAR ADC Technology0.13μm Resolution12-bit Active area0.096mm 2 Supply voltage1.2V Sample rate10MS/s SFDR (F SNR (F SNDR (F Power3mW FoM0.38pJ/c.s. 8

NTUEE ; Mixed-Signal IC Lab 陳信樹 Attain high conversion speed by adopting non-constant-radix switching method Compared to conventional non-binary designs, its DAC implementation is simpler. Experiment 3 - Low-Power High-Speed SAR ADC Technology90nm Resolution10-bit Chip area1.029mm 2 Supply voltage1.0V Sample rate40MS/s SFDR (F SNDR (F Power1.34mW FoM81.1fJ/c.s. 9

NTUEE ; Mixed-Signal IC Lab 陳信樹 Achieve high speed with a low-gain OPA by using digitally- assisted architecture, thus the OPAs have excellent power efficiency A simple gain-error self calibration method without external precise references requires only 168 calibration clock cycles. Ref [5] Experiment 4 - Low-Power High-Speed Pipelined ADC Technology90nm Resolution10-bit Active area0.21mm 2 Supply voltage1.2V Sample rate320MS/s SFDR (F SNDR (F Power42mW FoM0.44pJ/c.s. 10

NTUEE ; Mixed-Signal IC Lab 陳信樹 Digitally-Assisted High-Speed ADC Example (Experiment 4) Digitally assisted architecture is future trend to achieve excellent power efficiency. 10b, several hundreds MS/s Pipeline ADCs are widely used in wireless and cloud computing systems but suffer from OPA design in deep submicron CMOS processes.  Decreased OPA DC gain  Smaller signal swing 11

NTUEE ; Mixed-Signal IC Lab 陳信樹 Pipeline ADC Accuracy OPA gain  Less R o of MOSFET in advanced technologies  Reduced gain from each stage of OPA  More gain stages introduce poles and decrease bandwidth.  For 10b accuracy, the 1st stage MDAC requires 66dB OPA DC gain. Capacitor mismatch  Raw matching can attain 10b accuracy, not an issue! 12

NTUEE ; Mixed-Signal IC Lab 陳信樹 Closed-Loop Gain Error 13 For finite A, closed-loop gain A CL is smaller than ideal gain, 1/ . Gain error can be compensated by adjusting .

NTUEE ; Mixed-Signal IC Lab 陳信樹 Due to finite A, closed-loop gain is less than ideal value of 4.  adjustment is proposed to correct MDAC gain error. 14 MDAC Gain Error

NTUEE ; Mixed-Signal IC Lab 陳信樹 Proposed MDAC with a Calibration Capacitor A calibration capacitor, C cal, is added as a positive feedback to adjust   Closed-loop gain can achieve 10b accuracy with low DC gain A of 30dB. 15

NTUEE ; Mixed-Signal IC Lab 陳信樹 Self-Calibrated Algorithm (1) Self-calibrated procedure starts with the last stage MDAC. After MDAC is calibrated, it is treated as “ideal” MDAC. Ideal MDACs subtract 3V ref /8 and then multiply 4. Under-Calibration MDAC samples V ref /8 and then multiplies 4. 16

NTUEE ; Mixed-Signal IC Lab 陳信樹 Self-Calibrated Algorithm (2) – Gain Error Output is V ref /2 when no gain error Using successive approximation method with iterations, the closed-loop gain reaches 4 with 10b accuracy. 17

NTUEE ; Mixed-Signal IC Lab 陳信樹 Proposed ADC Architecture On-chip foreground analog self-calibrated technique Gain errors of first three stages are calibrated 18

NTUEE ; Mixed-Signal IC Lab 陳信樹 Calibration Step 128 calibration steps Each step affects 0.14 % of MDAC gain (~4) with OPA gain of 40dB 19

NTUEE ; Mixed-Signal IC Lab 陳信樹 Calibration Range C cal in this work can calibrate OPA with a minimum DC gain of 30dB 20

NTUEE ; Mixed-Signal IC Lab 陳信樹 OPA Use small L to increase bandwidth without considering gain Calibration mode has more compensation capacitance Simulation results: DC gain 40dB, closed-loop BW 1.36GHz 21

NTUEE ; Mixed-Signal IC Lab 陳信樹 Chip Micrograph 0.21mm 2 active area in 90 nm low-power CMOS 22

NTUEE ; Mixed-Signal IC Lab 陳信樹 Measured DNL Before calibration: +1.7 / -1.0 LSB After calibration: +0.7/-0.6 LSB Before calibration After calibration 23

NTUEE ; Mixed-Signal IC Lab 陳信樹 Measured INL Before calibration: +15.6/-15.2 LSB After calibration: +0.8/-0.9 LSB Before calibration After calibration 24

NTUEE ; Mixed-Signal IC Lab 陳信樹 Measured Dynamic Performance At low F in, SNDR ≈ 54.2dB, ENOB ≈ 8.7bit At Nyquist F in, SNDR ≈ 51.2dB, ENOB ≈ 8.2bit ERBW ≈ 160MHz 25

NTUEE ; Mixed-Signal IC Lab 陳信樹 Measured FFT SNDR ≈ 52.8dB and SFDR ≈ 57.8dB when F s = 320MHz and F in = 128MHz 26

NTUEE ; Mixed-Signal IC Lab 陳信樹 Measured Performance Summary JSSC09 [7]ISSCC07 [8]This Work Technology (nm) Calibration MethodForeground /Background Foreground Sample Rate (MS/s) Resolution (bit)10 DNL/INL (LSB)0.4/ /0.60.7/0.9 Peak SNDR (dB) SNDR (dB) at F s / SFDR (dB) Power (mW) FoM (fJ/c.-s.) Active Area (mm 2 ) NoteCalibration circuit is off- chip Input buffer power is included 27

NTUEE ; Mixed-Signal IC Lab 陳信樹 Summary A simple self-calibrated algorithm is proposed to correct gain error resulting from low gain OPA in deep submicron CMOS. The self-calibrated process does not require a precise external reference and can be done within only 168 clock cycles. Smallest active area of 0.21mm 2 in 90nm CMOS including calibration circuit The prototype ADC achieves 320MS/s conversion rate, 8.7 ENOB and only consumes 42mW. Nice power efficiency is obtained. Power efficiency is the key to high-speed ADC IC designs. 28

NTUEE ; Mixed-Signal IC Lab 陳信樹 Reference [1] [2] B. Murmann, "ADC Performance Survey ," [Online]. Available: [3] H. Chen et al., “A 1-GS/s 6-Bit Two-Channel Two-Step ADC in  m CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp , Nov [4] H. Chen et al., “A 3mW 12b 10MS/s Sub-Range SAR ADC” in IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers, Taipei, Taiwan, pp , Nov [5] H. Chen et al., “A 10b 320MS/s Self-Calibrated Pipeline ADC” in IEEE Asian Solid- State Circuits Conf. Dig. Tech. Papers, Peking, China, pp , Nov [6] B. Razavi and B. A. Wooley, “Design Techniques for High-Speed, High-Resolution Comparators,” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp , Dec [7] A. Verma and B. Razavi, ”A 10b 500MHz 55mW CMOS ADC,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp , Nov [8] B. Hernes et al.,”A 92.5mW 205MS/s 10b Pipeline IF ADC Implemented in 1.2V/3.3V 0.13  m CMOS,” ISSCC Dig. Tech. Papers, pp , Feb