A New Low Power Flash ADC Using Multiple-Selection Method Adviser: Dr.Hsun-hsiang Chen Presenter: Chieh-En Lo

Reference Wen-Ta Lee; Po-Hsiang Huang; Yi-Zhen Liao; Yuh-Shyan Hwang; Electron Devices and Solid-State Circuits, EDSSC IEEE Conference on Dec Page(s): Digital Object Identifier /EDSSC Electron Devices and Solid-State Circuits, EDSSC IEEE Conference on

Outline Introduction Modified flash adc architecture Proposed multiple-selection for flash adc Simulation and experimental results

introduction To reduce the power consumption for flash adc, we propose a multiple-selection design method to reduce the number of comparators Compared with the traditional 6-bit flash adc uses 63 comparators, our new proposed 6-bit modified flash adc architecture only uses 27 comparators therefore has smaller size and lower power consumption.

Modified flash adc architecture A. Comparator Vin>Vref, Vout 1 Vout! 0 Vin<Vref, Vout 0 Vout! 1

Modified flash adc architecture B. 4-bit modified flash adc

Proposed multiple-selection for flash adc

Simulation and experimental results