Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 1 ECE 747 Digital Signal Processing Architecture SoC Lecture – Working with Analog-to-Digital Converters April 17, 2007 W. Rhett Davis NC State University

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 2 Today’s Lecture l Introduction l Effective Number of Bits (ENOB) l Choosing the right ADC

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 3 Introduction l Thus far, we have focused on finding maximum and mean-square error (MSE) for our architectures. l How does this error relate to the real world (i.e. analog circuits)?

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 4 Signal-to-Noise Ratio l Signal-to-Noise Ratio (SNR) – Ratio of signal power to noise power l Typically, the performance of a system is specified in terms of SNR l How do we translate SNR into bits? l How do we translate MSE into SNR? Example: BER vs. SNR curves for a MIMO receiver Source: Ravi Jenkal

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 5 Modeling SNR l What is the noise in the SNR? » Typically band-limited additive white Gaussian noise l How do we model SNR? » Typically use a Gaussian random variable added to the input of the system l What scaling factor (K) do we use? » K should be equal to the standard deviation of the random variable, which is the square root of the variance » Note that the power of a Gaussian random variable is equal to the variance » For a discrete time systems, assume without loss of generality that T=1

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 6 Today’s Lecture l Introduction l Effective Number of Bits (ENOB) l Choosing the right ADC

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 7 Noise in ADCs l Analog-to-Digital Converters (ADCs) typically measure their noise performance in Effective Number of Bits (ENOB) l Sources of Noise: » Quantization noise » Analog circuit noise (thermal, shot, 1/f, etc.) » Distortion (not random, but can be modeled as noise)

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 8 Quantization Noise Source: Walden, JSAC1999 [1]

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 9 Example #1 l To achieve an SNR of 45 dB, what is the minimum number of bits required? l But what about the analog circuit noise and distortion in the ADC?

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 10 ADC Noise Measurements l SNDR – Signal-to-Noise Distortion Ratio » Ratio of signal power to noise power and harmonic distortion l SFDR – Spur-Free Dynamic Range » Ratio of largest harmonic amplitude to carrier amplitude l Example: 50 MS/s ADC with 20 MHz tone » SNDR = 54.6 dB, SFDR = 69 dB » Source: Ryu, Song, & Bacrania, ISSCC 2006 SFDR } (integral) SNDR

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 11 Effective Number of Bits (ENOB) l Typically, the largest sinusoid signal possible is used to measure SNDR, and therefore ENOB = [SNDR(dB)-1.76]/6.02 l ENOB is a better measure of how many bits you’re actually getting l SFDR is best used when the application is particularly sensitive to distortion l SFDR bits = [SFDR(dB)-1.76]/6.02

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 12 SNDR/SFDR vs. Stated Bits l Plots from Walden [1] show that ENOB is always less than the stated number of bits, but SFDR bits can be more or less than stated number (slightly more, on average)

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 13 Example #2 l Design a System with an SNR of 63 dB » Find ENOB l Suppose that the largest input signal is sin(ωt)+cos(ωt) » Find K 1

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 14 Example #2

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 15 Questions l For V signal (rms), we used a sinusoid with amplitude equal to the max value of the input signal, rather than integrate the input signal itself. Why? l Also, this covers noise for the ADC, but what about the rest of the analog front-end?

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 16 Example #3 l Suppose the same SNR and input signal from the last example l Suppose also the following: » the number of stated bits is 12 » a 3-σ noise margin should be added to the swing l Find K 2

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 17 Example #3

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 18 Today’s Lecture l Introduction l Effective Number of Bits (ENOB) l Choosing the right ADC

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 19 Why do we care? l We may make any assumption we like when designing a system about how many bits we have and what the SNR is… l …but how do we know if such an ADC even exists? How do we know if it is feasible to build the system we want to build?

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 20 Limits on ADC Performance l Aperture Jitter [2] » Determined by the amount of jitter  a in the sample clock » Main limitation of ADC performance » Leads to well-know figure of merit P=2 ENOB *f samp l Other contributors » Thermal noise (resistance in amplifier) » Comparator Ambiguity (delay in comparator, limited by transition frequency f T ) » Heisenberg Uncertainty Principle

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 21 Summary of ADC Performance [1] l Walden showed that P increase from roughly 1x10 11 in 1989 to 4x10 11 in 1997 [1] l One converter shown in 2006 ISSCC with P of 2.1x10 12 l Other limits on performance appear to less of a limiting factor [2]

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 22 Selecting an ADC l Different ADC architectures offer different bits/sample rates and power consumption l It’s helpful to review the most common types so that you navigate the papers and know what’s impressive (and what’s not) » Flash » Pipeline » Successive Approximation » Over-sampled

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 23 Flash & Pipeline ADC l Flash ADC » Also called “Direct- Conversion” ADC » Entire conversion performed at once in parallel » Very fast, very large, very power-hungry l Pipeline ADC » Like Flash, but broken into steps with DAC between Source: Maxim

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 24 Successive-Approximation ADC l Successive- Approximation Register (SAR) searches for digital value l Digital-to-Analog Converter DAC produces analog signal l Comparator compares DAC output to input voltage to produce control signal for next approximation l When done, SAR signals end of conversion (EOC) Source: Wikipedi a

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 25 Over-sampled ADC l Also called ΔΣ- or ΣΔ-ADC l Signal is over-sampled and converted to a smaller number of bits l A “decimation-filter” is used to achieve a larger number of bits at a lower rate l An Over-sampling ratio (OSR) of ~60 is common l Can be confusing to determine sample-rate (input or output?) Source: Wikipedia

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 26 Comparison of ADC Performance l Source: Le, Rondeau, & Reed, Signal Processing Magazine 2005 [2]

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 27 Comparison of ADC Power l Source: Le, Rondeau, & Reed, Signal Processing Magazine 2005 [2]

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 28 Power Figure-of-Merit (F) l F=(2 ENOB *f samp )/Power=P/Power l Source: Le, Rondeau, & Reed, Signal Processing Magazine 2005 [2]

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 29 References [1] R. H. Walden, “Analog-to-Digital Converter Survey and Analysis,” IEEE Journal on Selected Areas in Communications, vol. 17, no. 4, April [2] B. Le, T. W. Rondeau, J. H. Reed, C. W. Bostian, “Analog-to-Digital Converters: A Review of the Past, Present, and Future,” IEEE Signal Processing Magazine, Nov