Electronics for Telecommunications Complete time-domain behavioral model of Analog to Digital converter block using SIMULINK ® for advanced RF receiver architectures P OLITECNICO DI B ARI F.Cannone F.Cannone, G.Avitabile, G. Coviello,D. Cascella

Complete time-domain behavioral model of Analog to Digital converter block using SIMULINK ® for advanced RF receiver architectures Electronics for Telecommunications POLITECNICO DI BARI F. Cannone, G. Avitabile, G. Coviello, D. Cascella -Introduction -Proposed Model -Simulations - Conclusions Introduction Proposed Model Simulations Conclusions OUTLINE

Complete time-domain behavioral model of Analog to Digital converter block using SIMULINK ® for advanced RF receiver architectures Electronics for Telecommunications POLITECNICO DI BARI F. Cannone, G. Avitabile, G. Coviello, D. Cascella 1. Introduction2. Proposed model3. Simulations4. Conclusions SHA ADC DATA ACQUISITION SYSTEMMotivation Complete study at system level Take a choice about technology (SiGe, GaAS, etc), and circuital topology Tool of system level analysis after that the design choices have been made To drive the choice of the suitable RF architectures (SDR, direct RF Rx, etc.) To consider all the non idealities = to address the concerns limiting the performance Standard CAD models are lacking in utility (they do not model all the sources of errors)

Complete time-domain behavioral model of Analog to Digital converter block using SIMULINK ® for advanced RF receiver architectures Electronics for Telecommunications POLITECNICO DI BARI F. Cannone, G. Avitabile, G. Coviello, D. Cascella -Introduction -Proposed Model -Simulations - Conclusions Proposed Model OUTLINE

Complete time-domain behavioral model of Analog to Digital converter block using SIMULINK ® for advanced RF receiver architectures Electronics for Telecommunications POLITECNICO DI BARI F. Cannone, G. Avitabile, G. Coviello, D. Cascella 1. Introduction3. Simulations4. Conclusions2. Proposed model Developed in SIMULINK ® = advantages in terms of data manipulation, flexibility and simulation with other electronic subsystems. Model description The architecture of the model Model of SHA; Model of ADC (this work); Model of real clock (with jitter) The test bench Starting from the time-based simulation results, a set of Matlab files compute the typical FOM (SFDR, SNR, SNDR, ENOB etc.)

Complete time-domain behavioral model of Analog to Digital converter block using SIMULINK ® for advanced RF receiver architectures Electronics for Telecommunications POLITECNICO DI BARI F. Cannone, G. Avitabile, G. Coviello, D. Cascella 1. Introduction3. Simulations4. Conclusions2. Proposed model Sample and Hold and real clock behavioral models These blocks consider the following non idealities: offset voltage; gain error and gain linearity error; slew rate and acquisition time; aperture time, effective aperture delay time, aperture jitter and clock jitter; hold mode settling time and pedestal; droop rate; input feedthrough [5: Avitabile et al, MELECON 2008]

Complete time-domain behavioral model of Analog to Digital converter block using SIMULINK ® for advanced RF receiver architectures Electronics for Telecommunications POLITECNICO DI BARI F. Cannone, G. Avitabile, G. Coviello, D. Cascella 1. Introduction3. Simulations4. Conclusions2. Proposed model The architecture of the ADC model The core of the ADC, it performs the analog to digital conversion, modeling both the linear and the non linear errors associated with such operation Both based on Matlab files adopted by using the block “Embedded Matlab function” It models the non linear behavior of the ADC circuitry 1° block 2° block

Complete time-domain behavioral model of Analog to Digital converter block using SIMULINK ® for advanced RF receiver architectures Electronics for Telecommunications POLITECNICO DI BARI F. Cannone, G. Avitabile, G. Coviello, D. Cascella 1. Introduction3. Simulations4. Conclusions2. Proposed model The non linear behavior of the ADC circuitry It is important when the signal is close to V FS (real advanced ADC for SDR Rx) The non linear behavior is modeled by using the power series The inputs are the level of the first 5 harmonics. -> the Matlab file computes the first 5 coefficients y=a 1 *u+a 2 *u 2 +a 3 *u 3 +a 4 *u 4 +a 5 *u 5 1.to emulate a real ADC using the values from the simulations (i.e. Spectre, HB) or from the measurements 2.to evaluate the sensitivity to this feature of the overall ADC performance (i.e. the loss of resolution measured in terms of ENOB due to the large signal distortion) Two ways to use the model are possible:

Complete time-domain behavioral model of Analog to Digital converter block using SIMULINK ® for advanced RF receiver architectures Electronics for Telecommunications POLITECNICO DI BARI F. Cannone, G. Avitabile, G. Coviello, D. Cascella 1. Introduction3. Simulations4. Conclusions2. Proposed model The ADC core (1/2) It emulates a generic ADC: n and the FSR are variables, the user can define its own ADC It models the offset error and allows the user to set a parameter called DNL rms The DNL rms can be used to model the level of quality of the ADC. It is also possible to use the vector of the measured or simulated real thresholds. Two ways to use the model are possible: 1.to emulate a real ADC providing offset and the vector of thresholds or the DNL rms 2.to study the sensitivity of the conversion system to these errors

Complete time-domain behavioral model of Analog to Digital converter block using SIMULINK ® for advanced RF receiver architectures Electronics for Telecommunications POLITECNICO DI BARI F. Cannone, G. Avitabile, G. Coviello, D. Cascella 1. Introduction3. Simulations4. Conclusions2. Proposed model The ADC core (2/2) The outputs of the model are: 1. the quantized signal; 2. the codes expressed in decimal notation; 3. the overall conversion error The core of the Matlab file embedded is composed by the following instructions: LSB=FSRpp/(2^n); C_noise=DNL; offset=os; if u<-FSR, Analog=-FSR+LSB/2; elseif u>FSR, Analog=FSR- LSB/2; else Analog=u; end; AnalogShifted=Analog+FSR; R= AnalogShifted/LSB; Cod=floor(R)+1; V_th=thresholds; eml.extrinsic('wgn') DG=g; for k=1:Max V_th(k)=- FSR+k*LSB+DG(k)*(C_noise*LS B); end if (Analog-offset)<V_th(1), Y=-FSR+LSB/2; elseif (Analog-offset)>V_th(Max), Y=FSR-LSB/2; elseif (Analog-offset)<V_th(Cod-1), Y=-FSR+(Cod-1)*LSB-LSB/2; elseif (Analog-offset)<V_th(Cod), Y=-FSR+Cod*LSB-LSB/2; else Y=-FSR+(Cod+1)*LSB-LSB/2; end CODICI=(Y+FSR-LSB/2)/LSB+1; Code = CODICI; Out=Y; eq=u-Y; end

Complete time-domain behavioral model of Analog to Digital converter block using SIMULINK ® for advanced RF receiver architectures Electronics for Telecommunications POLITECNICO DI BARI F. Cannone, G. Avitabile, G. Coviello, D. Cascella -Introduction -Proposed Model -Simulations - Conclusions Simulations OUTLINE

Complete time-domain behavioral model of Analog to Digital converter block using SIMULINK ® for advanced RF receiver architectures Electronics for Telecommunications POLITECNICO DI BARI F. Cannone, G. Avitabile, G. Coviello, D. Cascella 1. Introduction4. Conclusions2. Proposed model3. Simulations The possible uses to study the impact of given ADC on the Rx to make the system level design of the A/D block setting the acceptable level of each non ideality The description of the test bench The inputs all the non-ideal parameters derived from a given ADC (a datasheet, measurements or transistor level simulations) or need to be determined before to start the design at circuit level The ouputs the FOMs: SFDR, SNR, SNDR, ENOB, INL,DNL, etc.

Complete time-domain behavioral model of Analog to Digital converter block using SIMULINK ® for advanced RF receiver architectures Electronics for Telecommunications POLITECNICO DI BARI F. Cannone, G. Avitabile, G. Coviello, D. Cascella 1. Introduction4. Conclusions2. Proposed model3. Simulations The description of the tests To validate the proposed model different simulations have been performed and we have verified that: 1.It emulates an ideal conversion block if all the parameters are set with the ideal values 2.There is a good agreement among the simulations and the expected results modifying separately each parameter taking all the other ones at the ideal values 3.It is able to emulate the behavior of a generic SHA [5] (keeping ideal the ADC part) 4.It is able to emulate the behavior of a generic ADC [this work] (keeping ideal the SHA part)

Complete time-domain behavioral model of Analog to Digital converter block using SIMULINK ® for advanced RF receiver architectures Electronics for Telecommunications POLITECNICO DI BARI F. Cannone, G. Avitabile, G. Coviello, D. Cascella 1. Introduction4. Conclusions2. Proposed model3. Simulations Some simulation results (1/2) We have used as inputs the parameters reported in [6]: 2 nd harmonic=-49.1dB, 3 rd harmonic=-43.7dB and DNL=0.5 LSB simulated ADC output power spectrumreported ADC output power spectrum [6] We have achieved a good agreement!

Complete time-domain behavioral model of Analog to Digital converter block using SIMULINK ® for advanced RF receiver architectures Electronics for Telecommunications POLITECNICO DI BARI F. Cannone, G. Avitabile, G. Coviello, D. Cascella 1. Introduction4. Conclusions2. Proposed model3. Simulations [6][Proposed model] Fin=202MHz, Fclk=600MHz SNDR = 40.0 dB Fin=202MHz, Fclk=600MHz SNDR = dB Fin=202MHz, Fclk=600MHz SFDR = 44.0 dB Fin=202MHz, Fclk=600MHz SFDR = dB Summary of the comparison Some simulation results (2/2) The proposed model can be used to test a generic ADC converter inserted in a receiver architecture! It is possible to use it in the second mode of operations, the system level design!

Complete time-domain behavioral model of Analog to Digital converter block using SIMULINK ® for advanced RF receiver architectures Electronics for Telecommunications POLITECNICO DI BARI F. Cannone, G. Avitabile, G. Coviello, D. Cascella -Introduction -Proposed Model -Simulations - Conclusions Conclusions OUTLINE

Complete time-domain behavioral model of Analog to Digital converter block using SIMULINK ® for advanced RF receiver architectures Electronics for Telecommunications POLITECNICO DI BARI F. Cannone, G. Avitabile, G. Coviello, D. Cascella 1. Introduction2. Proposed model4. Conclusions3. Experimental results A complete time-domain behavioral model of A to D converter based on its main characteristics has been shown to consider the FOM of an ADC, like SNR, ENOB and SFDR a complete test bench has been also developed and presented The proposed model is a complete tool in the system level study for addressing the design of the high speed converter in advanced architectures like SDR or undersampled direct RF Rx We have finally used the proposed model to determine, at the system level, the reasonable SHA and ADC blocks to be used in a SDR receiver that we are designing Conclusions and future works