6 - 1 Texas Instruments Incorporated Module 6 : Analogue Digital Converter C28x 32-Bit-Digital Signal Controller TMS320F2812

6 - 2 ADC Module  12-bit resolution ADC core  Sixteen analog inputs (range of 0 to 3V)  Two analog input multiplexers  Up to 8 analog input channels each  Two sample/hold units (for each input mux)  Sequential and simultaneous sampling modes  Auto sequencing capability - up to 16 auto conversions  Two independent 8-state sequencers  “Dual-sequencer mode”  “Cascaded mode”  Sixteen individually addressable result registers  Multiple trigger sources for start-of-conversion  External trigger, S/W, and Event Manager events

6 - 3 ADC Module Block Diagram (Cascaded Mode) 12-bit A/D Converter ResultSelect Result MUX RESULT0... RESULT1 RESULT2 RESULT15 CHSEL00 (state 0) CHSEL01 (state 1) CHSEL02 (state 2) CHSEL03 (state 3) CHSEL15 (state 15)... MAX_CONV1 Auto sequencer Start Sequence Trigger SOC EOC SoftwareEVAEVB Ext Pin (ADCSOC) Analog MUX MUXA ADCINA0 ADCINA1 ADCINA7... MUXB ADCINB0 ADCINB1 ADCINB7... S/HA S/HMUX S/HB

6 - 4 ADC Module Block Diagram (Dual-Sequencer mode)

6 - 5 F2812 ADC Clocking Example CLKIN (30 MHz) HSPCLK (150 MHz) ADCCLKPS bitsADCTRL30011b FCLK (25 MHz) FCLK = HSPCLK/(2*ADCCLKPS) ADCCLK = FCLK/(CPS+1) ADCCLK (25 MHz) CPS bitADCTRL1 0b To ADC pipeline sampling window ACQ_PS bits ADCTRL1 0111b Important: ADCCLK can be a maximum of 25 MHz! SYSCLKOUT (150 MHz) PLLCR DIV bits 1010b To CPU sampling window = (ACQ_PS + 1)*(1/ADCCLK) PCLKCR.ADCENCLK = 1 HISPCP HSPCLK bits 000b

6 - 6 Analog-to-Digital Converter Registers ADCTRL1 0x ADC Control Register 1 ADCTRL2 0x ADC Control Register 2 ADCMAXCONV 0x ADC Maximum Conversion Channels Register ADCCHSELSEQ1 0x ADC Channel Select Sequencing Control Register 1 ADCCHSELSEQ2 0x ADC Channel Select Sequencing Control Register 2 ADCCHSELSEQ3 0x ADC Channel Select Sequencing Control Register 3 ADCCHSELSEQ4 0x ADC Channel Select Sequencing Control Register 4 ADCASEQSR 0x ADC Auto sequence Status Register ADCRESULT0 0x ADC Conversion Result Buffer Register 0 ADCRESULT1 0x ADC Conversion Result Buffer Register 1 ADCRESULT2 0x00710A ADC Conversion Result Buffer Register 2 : : : : : : : : : : : : : : : : : : ADCRESULT14 0x ADC Conversion Result Buffer Register 14 ADCRESULT15 0x ADC Conversion Result Buffer Register 15 ADCTRL3 0x ADC Control Register 3 ADCST 0x ADC Status and Flag Register Register Address Description

6 - 7 ADC Control Register 1 - Upper Byte 0x reserved SUSMOD0 Emulation Suspend Mode 00 = [Mode 0] free run (do not stop) 01 = [Mode 1] stop after current sequence 10 = [Mode 2] stop after current conversion 11 = [Mode 3] stop immediately 11 ADC Module Reset 0 = no effect 0 = no effect 1 = reset (set back to 0 1 = reset (set back to 0 by ADC logic) by ADC logic) SUSMOD1 RESET ACQ_PS3 ACQ_PS2ACQ_PS1ACQ_PS0 Acquisition Time Prescale (S/H) Value = (binary+1) * Time dependent on the “Conversion Clock Prescale” bit (Bit 7 “CPS”) Clock Prescale” bit (Bit 7 “CPS”)

6 - 8 ADC Control Register 1 - Lower Byte 0x CPS CONT_RUN reserved Sequencer Mode 0 = dual mode 1 = cascaded mode 3 Continuous Run 0 = stops after reaching end of sequence end of sequence 1 = continuous (starts all over again from “initial state”) again from “initial state”) Conversion Prescale 0 = CLK / 1 1 = CLK / 2 SEQ_CASC reserved SEQ1_OVRD Sequencer Override (continuous run mode) 0 = sequencer pointer resets to “initial state” at end of MAX_CONVn at end of MAX_CONVn 1 = sequencer pointer resets to “initial state” after “end state” after “end state”

6 - 9 ADC Control Register 2 - Upper Byte 0x EVB_SOC_SEQ RST_SEQ1 Interrupt Enable (SEQ1) 0 = interrupt disable 1 = interrupt enable EVB SOC (cascaded mode only) 0 = no action 1 = start by EVB signal signal 11 Reset SEQ1 0 = no action 0 = no action 1 = immediate reset 1 = immediate reset SEQ1 to “initial state” SEQ1 to “initial state” Start Conversion (SEQ1) 0 = clear pending SOC trigger 1 = software trigger-start SEQ1 EVA SOC SEQ1 Mask Bit 0 = cannot be started by EVA trigger by EVA trigger 1 = can be started by EVA trigger by EVA trigger INT_ENA_SEQ1 INT_MOD_SEQ1 reserved EVA_SOC_SEQ1 SOC_SEQ1 Interrupt Mode (SEQ1) 0 = interrupt every EOS 1 = interrupt every other EOS

ADC Control Register 2 - Lower Byte 0x EXT_SOC_SEQ1 RST_SEQ2 External SOC (SEQ1) 0 = no action 1 = start by signal from ADCSOC pin from ADCSOC pin 3 Reset SEQ2 0 = no action 0 = no action 1 = immediate reset 1 = immediate reset SEQ2 to “initial state” SEQ2 to “initial state” Start Conversion (SEQ2) (dual-sequencer mode only) 0 = clear pending SOC trigger 1 = software trigger-start SEQ2 EVB SOC SEQ2 Mask bit 0 = cannot be started by EVB trigger by EVB trigger 1 = can be started by EVB trigger by EVB trigger INT_ENA_SEQ2INT_MOD_SEQ2 reserved EVB_SOC_SEQ2 SOC_SEQ2 Interrupt Enable (SEQ2) 0 = interrupt disable 1 = interrupt enable Interrupt Mode (SEQ2) 0 = interrupt every EOS 1 = interrupt every other EOS

ADC Control Register 3 0x Sampling Mode Select 0 = sequential sampling mode 1 = simultaneous sampling mode ADC Clock Prescale ADCCLKPS3 ADCCLKPS2 ADCCLKPS1 ADCCLKPS0 SMODE_SEL ADCRFDN ADCBGND ADCPWDN reserved ADC Reference Power Down 0 = powered down 1 = powered up ADC Bandgap Power Down 0 = powered down 1 = powered up ADC Power Down (except Bandgap & Ref.) 0 = powered down 1 = powered up

Maximum Conversion Channels Register 0x MAX_ CONV 2_2 MAX_ CONV 2_1 MAX_ CONV 2_0 MAX_ CONV 1_3 MAX_ CONV 1_2 MAX_ CONV 1_1 MAX_ CONV 1_0 reserved Cascaded Mode Dual Mode SEQ2SEQ1  Bit fields define the maximum number of auto conversions (binary+1)  Auto conversion session always starts with the “initial state” and continues sequentially until the “end state”, if allowed and continues sequentially until the “end state”, if allowed SEQ1 SEQ2 Cascaded SEQ1 SEQ2 Cascaded Initial state CONV00 CONV08 CONV00 End state CONV07 CONV15 CONV15

ADC Input Channel Select Sequencing Control Register Bits Bits 11-8 Bits 7-4 Bits 3-0 Bits Bits 11-8 Bits 7-4 Bits 3-0 0x CONV03 CONV02 CONV01 CONV00 ADCCHSELSEQ1 0x CONV07 CONV06 CONV05 CONV04 ADCCHSELSEQ2 0x CONV11 CONV10 CONV09 CONV08 ADCCHSELSEQ3 0x CONV15 CONV14 CONV13 CONV12 ADCCHSELSEQ4

Example - Sequencer “Start/Stop” Operation I 1, I 2, I 3 V 1, V 2, V 3 I 1, I 2, I 3 V 1, V 2, V 3 EVA Timer 1 EVAPWM System Requirements: Three auto conversions (I 1, I 2, I 3 ) off trigger 1 (Timer underflow)Three auto conversions (I 1, I 2, I 3 ) off trigger 1 (Timer underflow) Three auto conversions (V 1, V 2, V 3 ) off trigger 2 (Timer period)Three auto conversions (V 1, V 2, V 3 ) off trigger 2 (Timer period) Event Manager A (EVA) and SEQ1 are used for this example with sequential sampling mode

Example - Sequencer “Start/Stop” Operation (Continued) Bits  Bits  x V 1 I 3 I 2 I 1 ADCCHSELSEQ1 0x x x V 3 V 2 ADCCHSELSEQ2 MAX_CONV1 is set to 2 and Channel Select Sequencing Control Registers are set to: MAX_CONV1 is set to 2 and Channel Select Sequencing Control Registers are set to: Once reset and initialized, SEQ1 waits for a trigger Once reset and initialized, SEQ1 waits for a trigger First trigger three conversions performed: CONV00 (I 1 ), CONV01 (I 2 ), CONV02 (I 3 ) First trigger three conversions performed: CONV00 (I 1 ), CONV01 (I 2 ), CONV02 (I 3 ) MAX_CONV1 value is reset to 2 (unless changed by software) MAX_CONV1 value is reset to 2 (unless changed by software) SEQ1 waits for second trigger SEQ1 waits for second trigger Second trigger three conversions performed: CONV03 (V 1 ), CONV04 (V 2 ), CONV05 (V 3 ) Second trigger three conversions performed: CONV03 (V 1 ), CONV04 (V 2 ), CONV05 (V 3 ) End of second auto conversion session, ADC Results registers have the following values: End of second auto conversion session, ADC Results registers have the following values: RESULT0 I 1 RESULT3 V 1 RESULT1 I 2 RESULT4 V 2 RESULT2 I 3 RESULT5 V 3  User can reset SEQ1 by software to state CONV00 and repeat same trigger 1, 2 session SEQ1 keeps “waiting” at current state for another triggerSEQ1 keeps “waiting” at current state for another trigger

ADC Conversion Result Buffer Register 0x through 0x (Total of 16 Registers) With analog input 0V to 3V, we have: analog voltsconverted valueRESULTx 3.0FFFh1111|1111|1111| FFh0111|1111|1111| h0000|0000|0001| h0000|0000|0000|0000 MSB LSB

How do we Read the Result? Integer format RESULTx ACC Data Mem bit shift right xxxxxxxxxx xxxxxxxxxx0000 xxxxxxxxxx xx xx xx Example: read RESULT0 register #include "DSP281x_Device.h" void main(void) { Uint16 value;// unsigned Uint16 value;// unsigned value = AdcRegs.ADCRESULT0 >> 4; value = AdcRegs.ADCRESULT0 >> 4;} #include "DSP281x_Device.h" void main(void) { Uint16 value;// unsigned Uint16 value;// unsigned value = AdcRegs.ADCRESULT0 >> 4; value = AdcRegs.ADCRESULT0 >> 4;}

Lab 6: Two Channel Analogue Conversion initiated by GP Timer 1 AIM :  AD-Conversion of ADCIN_A0 and ADCIN_B0 initiated by GPT1-period of 0.1 sec.  ADCIN_A0 and ADCIN_B0 are connected to two potentiometers to control analogue input voltages between 0 and 3,0V.  no GPT1-interrupt-service  Auto-start of ADC with T1TOADC-bit !!  Use ADC-Interrupt Service Routine to read out the ADC results  Use main loop to show alternately the two results as light- beam on LED’s (GPIO port B7..B0)

Additional Registers to initialize Lab 6: General Purpose Timer Control ::GPTCONA Timer 1 Control:T1CON Timer 1 Period: T1PR Timer 1 Compare:T1CMPR Timer 1 Counter:T1CNT Interrupt Flag:IFR Interrupt Enable ask:IER ADC – Control 3:ADCTRL3 ADC – Control 2:ADCTRL2 ADC – Control 1:ADCTRL1 Channel Select Sequencer1:CHSELSEQ1 Max. number of conversions:MAXCONV ADC - Result 0:ADCRESULT0 ADC - Result 1:ADCRESULT1

Optional Lab6A Modify Lab-Exercise 4 ( ‘Knight-Rider’) : use the Analogue Input ADCIN0 to change use the Analogue Input ADCIN0 to change the frequency for the LED’s the frequency for the LED’s to add the ADC-setup use Lab6 as a start to add the ADC-setup use Lab6 as a start use a LED-frequency range between 50Hz and 1 Hz use a LED-frequency range between 50Hz and 1 Hz use (1) a linear or (2) a logarithm scale use (1) a linear or (2) a logarithm scale between F min and F max. between F min and F max.