Improving Single Slope ADC and an Example Implemented in FPGA with 16 Improving Single Slope ADC and an Example Implemented in FPGA with 16.7 GHz Equivalent Counter Clock Frequency Wu, Jinyuan Fermilab John Odeghe, Scott Stackley and Charles Zha Oct. 2011

Single Slope ADC ?= Wilkinson ADC Voltage Measurement  Voltage Measurement  Charge Measurement  Charge Measurement  INPUT TDC INPUT TDC Ramping Ref. Voltage In Wilkinson ADC, a capacitor is charged and then discharged. The two schemes are suitable for different applications. Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

Timing Uncertainty Confinement Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

A Common Implementation + CMP - Register Feeding CMP output to CK port of the register causes unnecessary challenges due to unconfined timing uncertainty: Must use Gray Code Counter. Must match propagation delays of all bits. + CMP - Register  Timing Uncertainty Gray Code Counter f Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

Improving Single Slope ADC and an Example in FPGA An Improvement + CMP - Hold Timing Uncertainty  Binary Counter f Feeding CMP output to D port of a FF reduces complexity: The counter is regular binary counter. No propagation delay matching is needed. Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

Doubling Digitizing Resolution + CMP - Hold Binary Counter f Confining timing uncertainty opens possibilities for further improvements: Resolution or sampling rate can be doubled easily. Improvements by a factor of 4, 8, 16, 32 etc. are possible. Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

Improvement, Further Improvement, Further, Further Improvement Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

Equivalent (Virtual) Clock Frequency + CMP - TDC V2 V1 T1 T2 Equivalent Clock Frequency = 1/DT Sampling Period   Crossing time between ramping reference voltage and input voltage is digitized. Finer timing measurement resolution is preferable. Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

Single Slope ADC Implemented in FPGA TDC R C R1 VREF Signal Source Shaper Signal Source Shaper The ramping reference voltage is generated from digital outputs of FPGA. The differential receivers for the FPGA input are used as comparator. TDC is implemented in the FPGA with approximately 60 ps bin width. Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

The Wave Union TDC Implemented in FPGA Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

TDC Using FPGA Logic Chain Delay Ultra-wide Bins This scheme uses low-cost FPGA devices  Fine TDC precision can be implemented in slow devices (e.g., 60 ps (LSB) in EP2C8T144C6).  FPGA internal structures cause uneven bin widths and ultra-wide bins.  CLK Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

The Wave Union TDC Scheme Regular TDC records only one transition 0: Hold 1: Unleash 1 Ultra-wide Bins Ultra-wide bins are sub-divided. + Wave Union TDC records multiple transitions. Wu Jinyuan, Fermilab, jywu168@fnal.gov May 2009

Improving Single Slope ADC and an Example in FPGA Wave Union? Photograph: Qi Ji, 2010 Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

Improving Single Slope ADC and an Example in FPGA TDC Test Results Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

Improving Single Slope ADC and an Example in FPGA The Test Hardware (2008) 2008 Altera Cyclone II + VME (~$1k) FPGA: EP2C8T144C6 ($28.80) 16 channel: 25 ps 2 channel: 10 ps 81 mW/channel Ref: Search “Wave Union TDC” Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

The Test Module & Result RMS 10ps Data Output via Ethernet FPGA with 8ch TDC 1 2 2 DNL Histogram LUT S 1 Two NIM inputs Auto-Calibration In(bin) Out(ps) BNC Adapter to add delay @ 140ps step. Wu Jinyuan, Fermilab, jywu168@fnal.gov May 2009

Improving Single Slope ADC and an Example in FPGA The Test Hardware (2011) www.altera.com 2011 Altera Cyclone III Starter Kit ($211+$50) FPGA: EP3C25F324C6N ($73.90) 32 channel: 30 ps (25 ps with linear power supply) 27 mW/channel Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

Delta T Between NIM Inputs FPGA Pulse Gen. TDC LeCroy 429A NIM FAN- OUT NIM To LVDS A TDC B TDC TDC C LeCroy 429A NIM FAN- OUT NIM To LVDS TDC TDC TDC TDC TDC channels internally ganged together has smallest standard deviation of time differences. Typical channel pairs sharing same fan-out unit has 30 ps RMS. Timing jitters of the fan-out units add to the measurement errors. Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

Improving Single Slope ADC and an Example in FPGA Specifications RMS Resolution (Delta T between two channels) 25 to 30 ps Same channel re-hit time interval 64 ns Temporary buffer capacity 128 hits/(4 ch)/(16 us) LVDS output port rate: 250 M bits/s/port Output capacity in each LDVS output port: 128 hits/(16 ch)/(16 us) Number of LVDS output ports: 1, 2, 3, 4/(16 ch) Power Consumption (Core only) 9.3 mW/channel Power Consumption (Total) 27 mW/channel Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

Improving Single Slope ADC and an Example in FPGA If You Want to Try www.altera.com THDB-H2G (HSMC to GPIO Daughter Board) $50 www.altera.com DK-START-3C25N Cyclone III FPGA Starter Kit $211 The FPGA on the Starter Kit is fairly powerful. More than 16 pairs LVDS I/O can be accessed via the daughter card. FPGA can fit 32 channels but implementing 16 channels is more practical given the I/O pairs. TDC data are stored in the RAM on the board and can be readout via USB. A good solution for small experiment systems as well as student labs. Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

Improving Single Slope ADC and an Example in FPGA ADC Test Results Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

A Demo Proto-type Module FPGA TDC R C R1 VREF+ 4xR2 VREF- VIN1+ VIN1- VIN2+ VIN2- FPGA Ethernet Interface Shaper TDC Shaper TDC Data Handling FPGA Connector Shaper TDC Shaper TDC A symmetrical summing circuit is used. Both the shaper output and the ramping reference are fully differential for low noise performance. Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

Single-ended and Differential Comparators FPGA TDC R C R1 VREF+ 4xR2 VREF- VIN1+ VIN1- VIN2+ VIN2- FPGA TDC R C R1 VREF Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

Test Result: 2 M samples/s, 12 bits INPUT Ramping Ref. Voltage Digitized Data Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

Improving Single Slope ADC and an Example in FPGA Noise/Pedestal Width FWHM ~ 3 bins FWHM ~ 2 bins Each bin in the histogram is (full scale)/4096. The measurement is taken when there is no input signal. There is no intrinsic noise preventing the comparator + TDC structure from being used as a 12-bit ADC Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

A Single-ended Test Module FPGA TDC R C R1 VREF A single-ended circuit is used. The ramp generation circuit and the input connectors are put on the proto-type board. The FPGA is on the Cyclone III Starter Kit evaluation board. Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

Test Result: 62.5 M Samples/s, ~7 bits The digitized data follow the input pulses as expected. Large noise can be seen in the digitized raw data partially due to single-ended scheme and partially due to long signal paths from the prototype board to the FPGA pins through the daughter card. Improvements can be anticipated with a better hardware. Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

Improving Single Slope ADC and an Example in FPGA Summary # of Bits Max. Sampling Rate: (TDC LSB = 60 ps) Test Results: 7 1/(128*60 ps) = 130 MHz 7 bits @ 62.5 MHz 8 1/(256*60 ps) = 65 MHz 9 1/(512*60 ps) = 32.6 MHz 10 1/(1024*60 ps) = 16.3 MHz 11 1/(2048*60 ps) = 8.1 MHz 12 1/(4096*60 ps) = 4 MHz 12 bits @ 2 MHz   Today, TDC in FPGA has reached fine time resolutions (<100 ps LSB). It becomes feasible using an FPGA plus a few passive components to implement the “fully digital” single slope ADC for most applications in high-energy physics and nuclear science. Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

The End Thanks

The Wave Union TDC using FPGA CLK Wave Union Launcher A A possible choice of the TDC can be a delay line based architecture called the Wave Union TDC implemented in FPGA. Shown here is an ASIC-like implementation in a 144-pin device. 18 Channels (16 regular channels + 2 timing reference channels). This FPGA (EP2C8T144C6) costs $28, $1.75/channel. (AD9222: $5.06/channel) LSB ~ 60 ps. RMS resolution < 25 ps. Power consumption 1.3W, or 81 mW/channel. (AD9222: 90 mW/channel) Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

Time Measurement Errors Due to Power Supply Noise Switching Power Supply Linear Power Supply Typical RMS resolution is 25-30 ps. Measurements with cleaner power (diamonds) is better than noisy power (squares). Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

Single Slope ADC Test: Waveform Digitization Shown here is a demo of a 6-bit single slope TDC. Sampling rate in this test is 22 MHz. Both leading and trailing reference ramps are used in this example. Nonlinear reference ramping is OK. The measurement can be calibrated. FPGA TDC TDC VREF 50 50 Input Waveform, Overlap Trigger & Reference Voltage 1000pF 100 Raw Data Calibrated Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

Historical Implementation in ASIC TDC DLL Clock Chain Coarse Time Counter c0 c1 HIT is used as CK input which creates unnecessary challenges. Coarse Time Register HIT Encoder Coarse Time Selection Logic Unnecessary Challenges = Extra Efforts + Reduced Performance Deadtime is unavoidable. Coarse time recording needs special care. Two array + encoder sets are needed for raising edge and falling edge. The register array must be reset for next event. The encoder must be re-synchronized with system clock in order to interface with readout stage. Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

Unnecessary Challenges Unnecessary for FPGA TDC 000 001 011 010 110 111 101 100 Gray Code Counter Coarse Time Counter Coarse Time Counter Coarse Time Counter In history, Gray code counters, double counters and dual registers + MUX are found in ASIC TDC coarse time counter schemes. Theses are unnecessary if the TDC is designed appropriately. In FPGA, a plain binary counter is sufficient. Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

Improving Single Slope ADC and an Example in FPGA Coarse Time Counter Coarse Time Counter Coarse Time HIT Fine Time Encoder Fine Time ENA The timing uncertainty between HIT and CLK is confined in the sampling register array. All the remaining logics are driven by the CLK signal. No special cares such as Gray code counter is needed for coarse time counter. CLK Hit Detect Logic Data Valid Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

A Better Implementation DLL Clock Chain HIT is used as D input. HIT Multi- Sampling Register Array Clock Domain Transfer 16-bit Encoder with Registered Outputs 16-bit Encoder with Registered Outputs Coarse Time Counter OR + Register DV EG T4..T0 TC Deadtimeless operation is possible. No special care is needed for coarse time. Both raising and falling edges are digitized with a single array + encoder set. No resetting is needed for the register array. The output is synchronized with the system clock and is ready to interface with readout stage. Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov

Digital Noise During Digitization ADC Shaper T1 V1 T2 V2 Noisy Clean Typical ADC devices creates noise that may interfere the analog circuits. The time interval for resetting of the common reference voltage may be noisy but analog signal is not sampled during it. There is no digital control activities during ramping up of the common reference voltage. Improving Single Slope ADC and an Example in FPGA Oct. 2011, Wu Jinyuan, Fermilab jywu168@fnal.gov