Www.kit.edu Directors Prof. Dr.-Ing. K.D. Müller-Glaser Prof. Dr.-Ing. J. Becker Prof. Dr. rer. nat. W. Stork Institute for Information Processing Technology.

Slides:

Advertisements

Similar presentations

1 PIANO+ OTONES WP3 SIGNAL PROCESSING ALGORITHMS.

Advertisements

Sumitha Ajith Saicharan Bandarupalli Mahesh Borgaonkar.

a By Yasir Ateeq. Table of Contents INTRODUCTION TASKS OF TRANSMITTER PACKET FORMAT PREAMBLE SCRAMBLER CONVOLUTIONAL ENCODER PUNCTURER INTERLEAVER.

1 Peak-to-Average Power Ratio (PAPR) One of the main problems in OFDM system is large PAPR /PAR(increased complexity of the ADC and DAC, and reduced efficiency.

David Hawkins Exascale Signal Processing for Millimeter-Wavelength Radio Interferometers David Hawkins

18/05/2015 Calice meeting Prague Status Report on ADC LPC ILC Group.

Test of LLRF at SPARC Marco Bellaveglia INFN – LNF Reporting for:

Implement a 2x2 MIMO OFDM-based channel measurement system (no data yet) at 2.4 GHz Perform baseband processing and digital up and down conversion on Nallatech.

Software-defined Radio using Xilinx (SoRaX) By: Anton Rodriguez & Mike Mensinger Advised by: Dr. In Soo Ahn & Dr. Yufeng Lu.

1 EQ2430 Project Course in Signal Processing and Digital Communications - Spring 2011 On phase noise and it effect in OFDM communication system School.

1 Final Presentation Project A – Spring 2009 High Speed Signal Processing Board Design Student: Nir Malka Lior Rom Instructor: Mike Sumszyk Duration: 1.

Virtual Architecture For Partially Reconfigurable Embedded Systems (VAPRES) Architecture for creating partially reconfigurable embedded systems Module.

Software Defined Radio Brad Freyberg, JunYong Lee, SungHo Yoon, Uttara Kumar, Tingting Zou Project Description System Design The goal of our project is.

Atacama Large Millimeter/submillimeter Array Expanded Very Large Array Robert C. Byrd Green Bank Telescope Very Long Baseline Array Spectrometer PDR John.

Xcube Recorder Chris Phillips. X-cube Data Logger 100% COTS hardware recorder 16 Gbps capability – 32 Gbps possible – External replaceable storage modules.

GallagherP188/MAPLD20041 Accelerating DSP Algorithms Using FPGAs Sean Gallagher DSP Specialist Xilinx Inc.

General Purpose FIFO on Virtex-6 FPGA ML605 board midterm presentation

Students: Oleg Korenev Eugene Reznik Supervisor: Rolf Hilgendorf

Wir schaffen Wissen – heute für morgen 24 August 2015PSI,24 August 2015PSI, Paul Scherrer Institut Status WP 8.2 RF Low Level Electronic Manuel Brönnimann.

Anthony Gaught Advisors: Dr. In Soo Ahn and Dr. Yufeng Lu Department of Electrical and Computer Engineering Bradley University, Peoria, Illinois May 7,

Implementing Adaptive Modulation in a Software-Defined Cognitive Radio Brandon Bilinski Computer Engineering Senior, Clemson University.

Reconfigurable Communication System Design

“ Analyzer for 40Gbit Ethernet “ (Bi-semestrial project) Executers: פריד מחאג ' נה Farid Mahajna Husam Kadan חוסאם קעדאן Instructor:

Wireless Communications

Software Defined Radio

DLS Digital Controller Tony Dobbing Head of Power Supplies Group.

The GNU in RADIO Shravan Rayanchu. SDR Getting the code close to the antenna –Software defines the waveform –Replace analog signal processing with Digital.

Booster Cogging Upgrades Craig Drennan, Kiyomi Seiya, Alex Waller.

Ultra-Wideband Research and Implementation By Jarrod Cook and Nathan Gove Advisors: Dr. Brian Huggins Dr. In Soo Ahn Dr. Prasad Shastry.

Using co-design techniques to increase the reliability of the Electronic control System for a Multilevel Power Converter Javier C. Brook, Francisco J.

September 19-20, 2007 A.Zaltsman EBIS RF Systems RF System Overview Alex Zaltsman September 19-20, 2007 DOE Annual Review.

Casper 2010Marc Torres Part 2: Building blocks for the next generation.

Orthogonal Frequency-Division Multiplexing Ideal system model for a time- invariant AWGN channelAWGN.

Features of the new Alibava firmware: 1. Universal for laboratory use (readout of stand-alone detector via USB interface) and for the telescope readout.

Digital Phase Control System for SSRF LINAC C.X. Yin, D.K. Liu, L.Y. Yu SINAP, China

ATtiny23131 A SEMINAR ON AVR MICROCONTROLLER ATtiny2313.

Digital Phase Control System for SSRF LINAC C.X. Yin, D.K. Liu, L.Y. Yu SINAP, China

Fast Fault Finder A Machine Protection Component.

ECE 353 Introduction to Microprocessor Systems Michael G. Morrow, P.E. Module #7 Assessment Quiz.

Adapting the LHC 1TFB electronic circuit to other equipments The candidates are: PS 1TFB PS TFB PS CBFB PSB TFB PSB 1TFB 1 Alfred Blas Working group meeting.

Student: Vikas Agarwal Guide: Prof H S Jamadagni

Final Presentation Winter Barak Shaashua Barak Straussman Supervisor: Idan Shmuel.

OFDM Based WLAN System Song Ziqi Zhang Zhuo.

1Ben ConstanceFONT Meeting 1st August 2008 ATF2 digital feedback board 9 channel board with replaceable daughter board (RS232 etc.) − Board will log data.

Omnisys There are a few different activities at Omnisys that may be of your interests. –New correlation spectrometer IC’s. –New FFT spectrometers –Future.

Digital Transceiver Implementation

Requirements for the PS/PSB TFB board 1 Alfred Blas Working group meeting - 07 December Sampling frequency 2.Required Delayed Clocks.

DDRIII BASED GENERAL PURPOSE FIFO ON VIRTEX-6 FPGA ML605 BOARD PART B PRESENTATION STUDENTS: OLEG KORENEV EUGENE REZNIK SUPERVISOR: ROLF HILGENDORF 1 Semester:

Poster Winter Barak Shaashua Barak Straussman Supervisor: Idan Shmuel.

M. TWEPP071 MAPS read-out electronics for Vertex Detectors (ILC) A low power and low signal 4 bit 50 MS/s double sampling pipelined ADC M.

4 BIT ADC BIT STREAM THE SOUND IS MEASURED (SAMPLED) AT REGULAR INTERVALS AND GIVEN A VALUE FROM 0 TO 15. THIS BINARY VALUE IS SENT TO A PARALLEL TO SERIAL.

Wideband Communications

ECE 101 Exploring Electrical Engineering Chapter 7 Data Acquisition Herbert G. Mayer, PSU Status 11/30/2015 Derived with permission from PSU Prof. Phillip.

Design of the 64-channel ASIC: update DEI - Politecnico di Bari and INFN - Sezione di Bari Meeting INSIDE, December 18, 2014, Roma Outline  Proposed solution.

Possible LLRF Configuration in ILC Sigit Basuki Wibowo LLRF Workshop, Shanghai - Nov 5, 2015.

Introduction to OFDM and Cyclic prefix

8.15 Noncoherent orthogonal Modulation(1) Noncoherent orthogonal modulation –If two signal is orthogonal and have the same energy during interval T, carrier.

Electronic and Information Engineering Department (DIEI) Slide 1 Euro Sereni (presenter) Giuseppe Baruffa, Fabrizio Frescura, Paolo Antognoni A SOFTWARE.

802.16e PHY Basic concepts By Timor Israeli.

Principios de Comunicaciones EL4005

I. Previously on IET.

SEU Mitigation Techniques for Virtex FPGAs in Space Applications

Simulink Implementation of a Cable Modem

Abelardo Jara-Berrocal Joseph Antoon Ph.D. Students

Combiner functionalities

Channel Estimation in OFDM Systems

UWB Receiver Algorithm

Channel Estimation in OFDM Systems

SKAMP Square Kilometre Array Molonglo Prototype

Presentation transcript:

Directors Prof. Dr.-Ing. K.D. Müller-Glaser Prof. Dr.-Ing. J. Becker Prof. Dr. rer. nat. W. Stork Institute for Information Processing Technology Karlsruhe Institute of Technology (KIT) CONDOR Plenary Berlin

Content Overview Project Status Milestones Status Hard-/Software Library Fault Tolerance of FPGA Hardware Demonstrator plans Prototyping Board and ADCs, DACs Demonstration Scenario KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 2 | © Institute for Information Processing Technology

Content Overview Project Status Milestones Status Hard-/Software Library Fault Tolerance of FPGA Hardware Demonstrator plans Prototyping Board and ADCs, DACs Demonstration Scenario KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 3 | © Institute for Information Processing Technology

Milestones KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 4 | © Institute for Information Processing Technology

Content Overview Project Status Milestones Status Hard-/Software Library Fault Tolerance of FPGA Hardware Demonstrator plans Prototyping Board and ADCs, DACs Demonstration Scenario KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 5 | © Institute for Information Processing Technology

Status Hard and Software Library KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 6 | © Institute for Information Processing Technology ComponentStatus Leon3 – Control SystemImplemented AHB Multilayer MatrixImplemented Modulation ASIPImplemented FFT ASIPImplemented iFFT ASIPImplemented Internal DAC interfaceImplemented External DAC interfaceImplemented Internal ADC interfaceImplemented External ADC interfaceImplemented Demodulation ASIPNot Implemented Yet Synchronisation ASIPNot Implemented Yet Frequency Offset CorrectionNot Implemented Yet Channel Correction ASIPNot Implemented Yet PRBS ModulesNot Implemented Yet 25GS/s Polyphase Halfband DecimatorImplemented

Modulation ASIP 2 Samples per clock Software configurable configuration Unmodulated Pilot tone BPSK QPSK QAM 16 QAM 64 Software configurable pilot tones *depends on max. Configuration table and pilot table size KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 7 | © Institute for Information Processing Technology FPGA TypeLUTRegistersBRAMMax. Frequency Virtex *212 MHz

(i)FFT ASIP Radix 2 (i)FFT ASIP 2 Samples per clock Max. 4 pipelined Radix 2 operations in a row Address calculation and Twiddle Factor calculation supports any FFT size KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 8 | © Institute for Information Processing Technology Max. FFT sizeLUTRegistersBRAMDSPMax. Freq MHz MHz MHz

DAC/ADC Module Prepares data to analogue interfaces Serialization/Deserialization Preamble Storage 2ers complement or binary Clipping/rounding Cyclic Prefix Parallelism configurable by generics KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 9 | © Institute for Information Processing Technology

Transmitter design for Demonstrator Ca. 2 Samples per clock per stream PRBS Generator Generates data to be send (8 Samples per clock) 4 parallel data streams 1 Modulation ASIP (QAM 16) 2 (i) FFT ASIPs DAC Module Configured for 4 data streams (8 samples per clock cycle) Cyclic Prefix about 8 samples (16 samples worst case) FPGA clock FPGA TypeLUTRegistersBRAMDSP XC6VHX380T % %14619%16418%

Receiver Special Components Digital Down Converter low pass filter to separate signal of interest decimation Synchronization time synchronization (results in wrong sample to start FFT with) frequency synchronization (results in orthogonal frequency problems) Correction local oscillator frequency offset (LOF offset) sampling oscillator frequency offset (SOF offset) KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 11 | © Institute for Information Processing Technology

Digital Down Converter 4 halfband filter stages passband: 781,25 MHz decimation factor: 16 KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 12 | © Institute for Information Processing Technology FPGA TypeLUTRegistersBRAMDSPFrequency Virtex MHz

Synchronisation Comparing autocorrelation and energy of received signal is used to determine the preamble. Phase difference of two consecutive, known symbols is used to compensate local frequency offset. KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 13 | © Institute for Information Processing Technology

Channel Correction Static version already implemented Correcting symbols with correction factor calculated by special symbol after preamble Planned Pilot symbol tracking Continuous feedback for correction factor KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 14 | © Institute for Information Processing Technology

Fault Tolerance Redundancy enabled by Modular design Multilayer metrix Spare ASIP instance ASIPs can be tested for functionality by software When disfunction is detected, ASIP will be replaced by spare ASIP of that type Broken ASIP might be repaired by reconfiguration (Single Event Upsets) Partial Reconfiguration Number of spare ASIPs can be broken down to one by using partial reconfiguration KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 15 | © Institute for Information Processing Technology

Fault Tolerance Redundancy using Partial Rekonfiguration KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 16 | © Institute for Information Processing Technology

Content Overview Project Status Milestones Status Hard-/Software Library Fault Tolerance of FPGA Hardware Demonstrator plans Prototyping Board and ADCs, DACs Demonstration Scenario KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 17 | © Institute for Information Processing Technology

Prototyping Boards Protyping Boards Estimated availability (October‘12) 2x XC6VHX380T 2x XC6VHX565T Sockets for Micram Ultra High Speed analogue converters DAC 25GS/s DAC 30GS/s Extension Boards with High Speed analogue converters DAC (MAX5881, 12-Bit, 4.3Gsps) ADC (ADC12D1800, 12-Bit, 3.6 GSPS) KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 18 | © Institute for Information Processing Technology

Demonstrator KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 19 | © Institute for Information Processing Technology

Vielen Dank für ihre Aufmerksamkeit Fragen? KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 20 | © Institute for Information Processing Technology - 11 Mai, 2011