DDR2 Serial Presence Detect Revision 1.1 (& DIMM Labels) Bill Gervasi Senior Technologist, Netlist Chairman, JEDEC Small Modules & DRAM Packaging Committees

Agenda What is a Serial Presence Detect (SPD)? How is it used in systems? Decoding the SPD revision system What is new in Revision 1.1 New DDR2 DIMM labels

What is the SPD? I 2 C-based serial EEPROM located on all JEDEC modules Describes the module characteristics Describes the DRAM characteristics

Using the SPD Read all module SPDs at boot time Each SPD has a unique I 2 C address wired Configure the memory controller based on contents of all SPDs SPD ID= X0 ID= X1 ID= X2 ID= X3 I 2 C serial bus DIMM Slot 0 DIMM Slot 1 DIMM Slot 2 DIMM Slot 3 Memory Controller (or South Bridge)

SPD Contents Memory and interface type Module configuration DRAM coarse parameters DRAM fine parameters Module features …

Module Parameters Standard module features –ECC bytes –Register on address lines –PLL on clock lines Unique module features –Fast PLL relock –Module height –Thermal characteristics

SPD Revision But SPDs change over time… how do I know what to read? Two part SPD Revision system –Encoding revision –Additions revision SPD Byte 62 = EncodingAdditions

SPD Revision Revision levels –Encoding level should only change in emergencies… tells how to interpret existing fields –Encoding level determines which bytes and bits are defined –Additions level never reverts or resets back to 0 SPD interpretation –BIOS must reject modules with encoding level higher than it understands –BIOS should accept higher additions levels but only use the fields it knows how to decode!

New in Revision 1.1 DDR2 SPD Revision 1.1 ADDITIONS –Address/command parity (SPD[11]) –Number of registers & PLLs (SPD[21]) –High temperature operation capabilities (SPD[47,49]) –Thermal coefficients (SPD[47-61]) These fields are used to determine when the system has to throttle memory access

Parity Function, Register & PLL Count Address/command parity function –SPD[12] bit 2: single bit flag (yes or no) Register count & PLL count –SPD[21] bits 0,1 = Number of registers –SPD[21] bits 2,3 = Number of PLLs –Used in power calculations

Extended DRAM Temp Features Operation above the standard 85ºC case –SPD[47] bits 4-7 = operation up to 113ºC Double rate refresh required for high temp –SPD[49] bit 1 = yes/no High Temperature Self Refresh Entry –SPD[49] bit 0 = yes/no –If yes, controller may set DRAM mode register HT SR bit then enter SR while T CASE > 85ºC

Thermal Effects, DRAMs SPD MODE IDD0 IDD2N/Q IDD2P IDD3N IDD3P IDD5B IDD7 MEANING Delta from ambient due to activation & precharge Delta from ambient due to precharge standby Delta from ambient due to precharge powerdown Delta from ambient due to active standby Delta from ambient due to fast powerdown exit Delta from ambient due to slow powerdown exit Delta from ambient due to burst autorefresh Delta from ambient due to all bank interleave read

Thermal Effects, DRAMs  T for IDD4R versus IDD4W –SPD[55] bits 1-7 = change from ambient due to open page burst read –SPD[55] bit 0 = IDD4W IDD4R –SPD[47] bits 0-3 = delta between IDDRW & R In other words… –Calculate IDD4R, then add or subtract the delta for IDD4W depending on whether 55.0 = 1 or 0

Thermal Effects, Registers Thermal resistance of register package –SPD[59] for all register packages  T from ambient for registers –SPD[61] bits 1-7 = temp rise for each register Register toggle rate –SPD[61] bit 0 = 1T or 2T addressing (command every clock or every other clock) Number of registers on the DIMM –SPD[21] bits 0,1 have the number of registers

Thermal Effects, PLLs Thermal resistance of PLL package –SPD[58] for all register packages  T from ambient for registers –SPD[60] for each register Number of PLLs on the DIMM –SPD[21] bits 2,3 have the number of PLLs

New DIMM Labels

New Standard Labels Dual-channel memory systems enter the mainstream Need a simple mechanism for matching End-user friendly; no need for IT degree ?

DIMM Label Spec Example: 1GB 2Rx8 PC2-5300U A1 1GB = Total module capacity 2Rx8 = Number of ranks of memory & chip width PC = Speed grade in MB/s across DIMM U = Module type (unbuffered, registered, etc.) 444 = CAS latency–tRCD–tRP performance grade 11 = SPD revision (encoding + additions) A1 = Standard board layout and revision

Thank You ___ Q & A