JAZiO ™ IncorporatedPlatform JAZiO ™ Supplemental SupplementalInformation

JAZiO ™ IncorporatedPlatform Alternating References Larger differential signal when signal changes Reduces signal slew rate to achieve the same differential swing Instead of static VREF, JAZiO uses dynamic Voltage/Timing Reference (VTR) VTR Data Input VREF Pseudo Differential JAZiO Data Input

JAZiO ™ IncorporatedPlatform Voltage to Time Domain Transposition Change No Change pp D D Vref Vol Voh Full Differential JAZiO Pseudo Differential JAZiO transposes the voltage domain to the time domain, since signal binary is defined in the time domain. JAZiO binary margin is more dependent on transition time rather than voltage swing. Change vs No Change GapPeak to Peak DifferenceAbove or Below Reference

JAZiO ™ IncorporatedPlatform Change /No Change Concept Comp A Data In VTR Data In Comp A No Change This band is based on process mismatch (device W, L, etc.), reflection or overshoot (discontinuity, termination, inductance, etc.). 3 Case 3: Comp A remains High (weakly) while the Data Output retains the previous data Case 1: Comp A amplifies the change and the data passes through the Steering Logic Change 1 The time gap is used by the steering logic to pass the change or block the no-change from reaching the data output 1

JAZiO ™ IncorporatedPlatform I/O Interface Power Comparison The system can be optimized to achieve: Cost reduced package and lower system cost or Higher integration: more pins for more performance Giga Bytes/Second Power (mW) I/O Power For 15pf & 30pf Load 1.8V Vtt JAZiO-1000 JAZiO-2000 JAZiO™ (x16) Current Single Ended Technologies

JAZiO ™ IncorporatedPlatform Reduced noise Improved margins Improved scalability I/O Interface Transition Time Comparison Transition Time (nS) Bits per Second per Pin (b/S) 10M 100M 1G 10G EDO SDRAM SDRAM-100 DDR RDRAM JAZiO™ DDR Better

JAZiO ™ IncorporatedPlatform Noise JAZiO works best with slow edges (use the entire Bit Time!) JAZiO works with small transition levels (differential sensing) Works with any Termination Scheme (Series, Parallel, Single, Dual, Source and even none in some applications) JAZiO is entirely common-mode

JAZiO ™ IncorporatedPlatform VTT Signal VTR VTT Signal VREF 1.VSSQ noise between signal and VREF 2.VTT noise and/or VTT mismatch on either end 3.VREF impedance to Signal impedance mismatch Power Supply Noise Issues JAZiO Pseudo Differential

JAZiO ™ IncorporatedPlatform Slower transition generates less noise in JAZiO 2.Smaller transition generates less noise in JAZiO 3.VTRs are isolated by VSS to eliminate noise variations Environmental Noise Issues VTT Signal VTR JAZiO VTT Signal VREF Pseudo Differential Board dimensions have not shrunk as rapidly as on-chip dimensions

JAZiO ™ IncorporatedPlatform On Hard No Change (Low Victim) 0.8V CASE JAZiO Slowly Turn On Change (High to Low Victim) CASE 2 VREF 2 1 Pseudo Differential Noise (No Change) Noise (Change) No Noise (Change) No Noise (No Change) Environmental Noise Issues Wider Band Narrower Band 0.5V Less Noise; More Signal More Noise; Less Signal

JAZiO ™ IncorporatedPlatform DRAM Application Example JAZiO can be used between Controller and DRAM to achieve even greater than 2 GBit/pin/sec bandwidth JAZiO’s signaling technology allows bus expansion in both depth and width. No restriction on bus protocol or definition JAZiO is a low latency interface JAZiO makes implementation easier and takes the burden off of meeting set-up time, hold time, and rise/fall times. Single cycle power-up initialization allows user to fully utilize standby/sleep mode Low power and wide operating frequency improves DRAM cost JAZiO’s small voltage swing and slow transition time allows multiple slots with terminations at both ends. Easily adaptable for large memory systems (like servers) Better performance and scalability CPU Controller L2 DRAM JAZiO

JAZiO ™ IncorporatedPlatform Clock Source Upper Address & Control Lines Lower Data Lines VTR0 VTR1 Lower Address & Control Lines 5 Bit Addr & Ctrl VTR0 & VTR0 Data VTR1 & VTR1 Data Upper Data Lines VTT CONTROLLERCONTROLLER DRAM Clock

JAZiO ™ IncorporatedPlatform Read Cycle 8-Bit Burst

JAZiO ™ IncorporatedPlatform Write Cycle 8-Bit Burst

JAZiO ™ IncorporatedPlatform Read, Read,Write, Read Burst VTR0 VTR1 CS/RAS CAS/WE ADR 0:7/ ADR 8:15 I/O 0:17 10 Cycles CLK

JAZiO ™ IncorporatedPlatform Data 0:8 Lower Address & Control Lines Data 9:17 VTR0 Clock Source VTT VTR1 VTT CONTROLLERCONTROLLER DRAM VTR2 Data VTR2 & VTR2 Data VTT 5 Bit Addr & Ctrl VTR0 & VTR0 Data VTR1 & VTR1 Data DRAM Data 18:26 Data 27:35 VTT 5 Bit Addr & Ctrl Clock VTT Clock Upper Address & Control Lines

JAZiO ™ IncorporatedPlatform CPU to SRAM Application Example JAZiO can be used between CPU and SRAM (L2) to achieve huge bandwidth and low latency JAZiO bus can run at the same frequency as the internal CPU clock and include DDR (2 Gbit/sec per pin) Might use no terminations due to slow transitions and short lengths Control pin count on Back Side Bus Easily adaptable to support multiple cache sizes More external cache, less internal cache  smaller CPU die sizes No restriction and full differentiation on bus protocol and definition Better performance and scalability JAZiO CPU Controller L2 DRAM JAZiO

JAZiO ™ IncorporatedPlatform Front Side Bus JAZiO can be used in a proprietary bus between CPU and the Northbridge to achieve even greater than 16 GBytes/sec bandwidth. JAZiO bus can essentially run at the same frequency as the internal CPU clock with DDR. No restriction and full differentiation on bus protocol and definition. Lower cost in packaging and heat sink requirements due to reduced pins and power. Better performance and scalability. JAZiO CPU JAZiO Northbridge L2 DRAM

JAZiO ™ IncorporatedPlatform Front Side Bus JAZiO can be used in a proprietary bus between CPU(s) and the Controller(s) to achieve many GBytes/sec bandwidth No restriction and full differentiation on bus protocol and definition MP snoopy bus or very high speed point-to-point For point-to-point, JAZiO bus can run at the same frequency as the internal CPU clock and include DDR (2 Gbit/sec per pin) Keep pin count growth and bus power under control Lower cost in packaging and heat sink requirements due to reduced pins and power Better performance and scalability Controller DRAM CPU L2 JAZiO

JAZiO ™ IncorporatedPlatform Internal Application Example (SOC, Embedded, Etc.) JAZiO is well suited for large internal bus structures (SOC), which have greater than 2 pf/line loading. JAZiO uses ~0.3V swing with small transmitters and receivers to easily substitute traditional full swing buses. JAZiO also scales as the technology changes (process, voltage, etc.). JAZiO makes implementation easier and takes the burden off of meeting set-up time, hold time, and rise/fall times. JAZiO requires no PLL or DLL or repeater circuitry. JAZiO can support multiple frequencies on a given bus structure, it can be used synchronously or asynchronously, can support multiple supply voltages on the same bus, thus allowing the user flexibility in optimizing any implementation. JAZiO