1 Worst-case Delay Analysis Considering the Variability of Transistors and Interconnects Takayuki Fukuoka, Tsuchiya Akira and Hidetoshi Onodera Kyoto University

2 Outline Motivation Worst-delay Analysis Classification of the Worst-delay Direction Conclusions

3 Motivation Technology scaling Increasing significance of variation Transistor and Interconnect variations affect delay variation Gate length, width etc. Metal width, ILD (inter layer dielectric) etc. Worst-delay corner depends on many parameters (Drive strength, Interconnect length etc.) Where is the worst-delay corner? How the corner changes?

4 Outline Motivation Worst-delay Analysis Interconnect Model Delay Model Worst-delay Corner Case Study Classification of the Worst-delay Direction Conclusions

5 Interconnect Model Interconnect structure variation (W, T and H) Pitch (S+W) is constant R, C and RC variations Not statistically independent of R and C variations As R increases, C decreases Cross section model for interconnects

6 R and C variations C variation[%] R variation[%] C max R max RC max ITRS nm Intermediate W, T, H 3σ=20% C max Interconnect becomes thick (W+, T+, H-) R and RC max Interconnect becomes thin (W-, T-, H-) Wider Spacing C variation decreases R variation does not change C variation[%] R variation[%] C max R max RC max S=WS=3W Opposite direction

7 Delay Model [S.Sakurai, IEEE trans. ’93] Delay formula of a RC distributed line Transistor variation Rtr variation Interconnect variation W, T, H variations Every part of the interconnect is uniformly fluctuated

8 Delay Variation Model Delay is linear combination of parameters W, T, H and Rtr are normally distributed Delay is normally distributed Statistical worst-delay is : nominal value : standard deviation

9 width thickness Normalization Worst-delay corner ( ) Worse-delay Corner relative values of sensitivity coefficients (W-14%, T-14%)

10 Case Study ITRS nm High performance model: Intermediate Interconnect: W, T, H and Rtr variations: Realistic Drive strength and Interconnect length Optimally-buffered interconnect length: 94um Optimal drive strength: 32X buffer Optimum length

11 Experimental Results (drive strength) Drive strength: 1X Drive strength: 32X width thickness 10% 7% -2% -8% Opposite direction

12 Experimental Results (Spacing) Spacing: S=3W Drive strength: 1X Wider spacing W and T effects (C effect) become small Worst-delay corner depends on many parameters (drive strength, spacing, etc.) Spacing: S=W Drive strength: 1X

13 Outline Motivation Worst-delay Analysis Classification of the Worst-delay Direction Conclusions

14 Idea of Classification Worst-delay Direction Interconnect becomes thick (W+, T+) or thin (W-, T-) Dominant factor C: interconnect thick delay increases R, RC: interconnect thin delay increases We compare the proportion of each term The largest term is the dominant factor

15 Example of C-dominant case C dominant Second term (R tr C) > Forth term (RC L ) Drive strength is small. As interconnect becomes thick (C increases), delay increases. Rtr also affects delay RC dominant Long interconnect As Interconnect becomes thin (R increases), delay increases. Drive strength: １ X Spacing: S=W C dominant RC dominant

16 Example of R-and RC-dominant case large drive strength R tr decreases and C L increases (R tr C decreases and RC L increases) As interconnect becomes thin, delay increases. Drive strength:32X Spacing: S=W Optimum drive strength RC dominant R dominant

17 Intermediate vs. Global Intermediate (thin) Global (thick) Global: R is small R and RC dominant regions become smaller. The boundary of each dominant region changes depending on layer

18 Minimum Spacing vs. Wider Spacing Spacing: S=WSpacing: S=3W Wider spacing C variation becomes smaller. C dominant regions become smaller.

19 Conclusions We propose a criterion for classifying the worst-delay direction Worst-delay corner is context-dependent Small drive strength: Thicker interconnect worst-delay Large drive strength or long interconnect: Thinner interconnect worst-delay This criterion is used as a guideline for the selection of interconnect parasitic values used for the worst-delay calculation.